Added equivalence checking tests for DSP multiplier and DSP SIMD inference

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

ql-qlf-plugin/tests/qlf_k6n10f/dsp_mult/dsp_mult.tcl

diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/dsp_mult/dsp_mult.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/dsp_mult/dsp_mult.tcl
index 75acb10..b653836 100644
--- a/ql-qlf-plugin/tests/qlf_k6n10f/dsp_mult/dsp_mult.tcl
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/dsp_mult/dsp_mult.tcl
@@ -1,3 +1,29 @@
+# For some tests the equiv_induct pass seems to hang if opt_expr + opt_clean
+# are not invoked after techmapping. Therefore this function is used instead
+# of the equiv_opt pass.
+proc check_equiv {top} {
+    hierarchy -top ${top}
+
+    design -save preopt
+    synth_quicklogic -family qlf_k6n10f -top ${top}
+    design -stash postopt
+
+    design -copy-from preopt  -as gold A:top
+    design -copy-from postopt -as gate A:top
+
+    techmap -wb -autoproc -map +/quicklogic/qlf_k6n10f/cells_sim.v
+    yosys proc
+    opt_expr
+    opt_clean
+
+    async2sync
+    equiv_make gold gate equiv
+    equiv_induct equiv
+    equiv_status -assert equiv
+
+    return
+}
+
 yosys -import
 if { [info procs quicklogic_eqn] == {} } { plugin -i ql-qlf}
 yosys -import  ;# ingest plugin commands
@@ -7,29 +33,29 @@
 
 set TOP "mult_16x16"
 design -load read
-hierarchy -top $TOP
-synth_quicklogic -family qlf_k6n10f -top $TOP
-yosys cd $TOP
+check_equiv ${TOP}
+design -load postopt
+yosys cd ${TOP}
 select -assert-count 1 t:QL_DSP2
 
 set TOP "mult_20x18"
 design -load read
-hierarchy -top $TOP
-synth_quicklogic -family qlf_k6n10f -top $TOP
-yosys cd $TOP
+check_equiv ${TOP}
+design -load postopt
+yosys cd ${TOP}
 select -assert-count 1 t:QL_DSP2
 
 set TOP "mult_8x8"
 design -load read
-hierarchy -top $TOP
-synth_quicklogic -family qlf_k6n10f -top $TOP
-yosys cd $TOP
+check_equiv ${TOP}
+design -load postopt
+yosys cd ${TOP}
 select -assert-count 1 t:QL_DSP2
 
 set TOP "mult_10x9"
 design -load read
-hierarchy -top $TOP
-synth_quicklogic -family qlf_k6n10f -top $TOP
-yosys cd $TOP
+check_equiv ${TOP}
+design -load postopt
+yosys cd ${TOP}
 select -assert-count 1 t:QL_DSP2
 

ql-qlf-plugin/tests/qlf_k6n10f/dsp_simd/dsp_simd.tcl

diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/dsp_simd/dsp_simd.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/dsp_simd/dsp_simd.tcl
index dd06114..0599d95 100644
--- a/ql-qlf-plugin/tests/qlf_k6n10f/dsp_simd/dsp_simd.tcl
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/dsp_simd/dsp_simd.tcl
@@ -1,3 +1,29 @@
+# For some tests the equiv_induct pass seems to hang if opt_expr + opt_clean
+# are not invoked after techmapping. Therefore this function is used instead
+# of the equiv_opt pass.
+proc check_equiv {top} {
+    hierarchy -top ${top}
+
+    design -save preopt
+    synth_quicklogic -family qlf_k6n10f -top ${top}
+    design -stash postopt
+
+    design -copy-from preopt  -as gold A:top
+    design -copy-from postopt -as gate A:top
+
+    techmap -wb -autoproc -map +/quicklogic/qlf_k6n10f/cells_sim.v
+    yosys proc
+    opt_expr
+    opt_clean
+
+    async2sync
+    equiv_make gold gate equiv
+    equiv_induct equiv
+    equiv_status -assert equiv
+
+    return
+}
+
 yosys -import
 if { [info procs quicklogic_eqn] == {} } { plugin -i ql-qlf}
 yosys -import  ;# ingest plugin commands
@@ -8,8 +34,8 @@
 set TOP "simd_mult"
 design -load read
 hierarchy -top $TOP
-synth_quicklogic -family qlf_k6n10f -top $TOP
-yosys cd $TOP
+check_equiv ${TOP}
+design -load postopt
 select -assert-count 0 t:dsp_t1_20x18x64
 select -assert-count 0 t:dsp_t1_10x9x32
 select -assert-count 1 t:QL_DSP2
@@ -17,7 +43,8 @@
 set TOP "simd_mult_inferred"
 design -load read
 hierarchy -top $TOP
-synth_quicklogic -family qlf_k6n10f -top $TOP
+check_equiv ${TOP}
+design -load postopt
 yosys cd $TOP
 select -assert-count 0 t:dsp_t1_20x18x64
 select -assert-count 0 t:dsp_t1_10x9x32
@@ -26,7 +53,8 @@
 set TOP "simd_mult_odd"
 design -load read
 hierarchy -top $TOP
-synth_quicklogic -family qlf_k6n10f -top $TOP
+check_equiv ${TOP}
+design -load postopt
 yosys cd $TOP
 select -assert-count 0 t:dsp_t1_20x18x64
 select -assert-count 0 t:dsp_t1_10x9x32
@@ -35,7 +63,8 @@
 set TOP "simd_mult_conflict"
 design -load read
 hierarchy -top $TOP
-synth_quicklogic -family qlf_k6n10f -top $TOP
+check_equiv ${TOP}
+design -load postopt
 yosys cd $TOP
 select -assert-count 0 t:dsp_t1_20x18x64
 select -assert-count 0 t:dsp_t1_10x9x32