systemverilog-plugin: fix sometimes wrong handle of ranges in port wire

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>

systemverilog-plugin/UhdmAst.cc

diff --git a/systemverilog-plugin/UhdmAst.cc b/systemverilog-plugin/UhdmAst.cc
index febcb9d..1d9689e 100644
--- a/systemverilog-plugin/UhdmAst.cc
+++ b/systemverilog-plugin/UhdmAst.cc
@@ -4292,7 +4292,7 @@
                 }
                 delete node;
             });
-            visit_one_to_many({vpiRange}, actual_h, [&](AST::AstNode *node) { current_node->children.push_back(node); });
+            visit_one_to_many({vpiRange}, actual_h, [&](AST::AstNode *node) { packed_ranges.push_back(node); });
             shared.report.mark_handled(actual_h);
             break;
         case vpiPackedArrayNet:
@@ -4300,7 +4300,7 @@
             shared.report.mark_handled(actual_h);
             break;
         case vpiArrayVar:
-            visit_one_to_many({vpiRange}, actual_h, [&](AST::AstNode *node) { current_node->children.push_back(node); });
+            visit_one_to_many({vpiRange}, actual_h, [&](AST::AstNode *node) { unpacked_ranges.push_back(node); });
             shared.report.mark_handled(actual_h);
             break;
         case vpiEnumNet: