Merge pull request #518 from antmicro/kr/split_line_column
systemverilog-plugin: split line and column in uhdmast_assert_log
diff --git a/systemverilog-plugin/UhdmAst.cc b/systemverilog-plugin/UhdmAst.cc
index 78b4869..0f5d120 100644
--- a/systemverilog-plugin/UhdmAst.cc
+++ b/systemverilog-plugin/UhdmAst.cc
@@ -1524,13 +1524,25 @@
return ::systemverilog_plugin::const2ast(val.value.str, caseType, false);
} else {
auto size = vpi_get(vpiSize, obj_h);
- if (size == 0) {
- auto c = AST::AstNode::mkconst_int(atoi(val.value.str), true, 32);
- c->is_unsized = true;
- return c;
- } else {
- return ::systemverilog_plugin::const2ast(std::to_string(size) + strValType + val.value.str, caseType, false);
+ std::string size_str;
+ if (size > 0) {
+ size_str = std::to_string(size);
+ } else if (strValType == "\'b") {
+ // probably unsized unbased const
+ // but to make sure parse vpiDecompile
+ auto decompile = vpi_get_str(vpiDecompile, obj_h);
+ if (decompile && !std::strchr(decompile, 'b')) {
+ // unsized unbased
+ // we can't left size_str empty, as then yosys parses this const as 32bit value
+ size_str = "1";
+ }
}
+ auto c = ::systemverilog_plugin::const2ast(size_str + strValType + val.value.str, caseType, false);
+ if (size <= 0) {
+ // unsized unbased const
+ c->is_unsized = true;
+ }
+ return c;
}
}
return nullptr;
@@ -1742,6 +1754,9 @@
visit_one_to_one({vpiElemTypespec}, obj_h, [&](AST::AstNode *node) {
if (node && node->type == AST::AST_STRUCT) {
auto str = current_node->str;
+ // unnamed array of named (struct) array
+ if (str.empty() && !node->str.empty())
+ str = node->str;
node->cloneInto(current_node);
current_node->str = str;
delete node;
@@ -2012,7 +2027,7 @@
current_node->children.push_back(pair.second);
}
} else {
- log_warning("Removing unused module: %s from the design.\n", pair.second->str.c_str());
+ log_warning("Removing unelaborated module: %s from the design.\n", pair.second->str.c_str());
// TODO: This should be properly erased from the module, but it seems that it's
// needed to resolve scope
delete pair.second;
diff --git a/systemverilog-plugin/tests/Makefile b/systemverilog-plugin/tests/Makefile
index 94f6563..dcdbafd 100644
--- a/systemverilog-plugin/tests/Makefile
+++ b/systemverilog-plugin/tests/Makefile
@@ -35,3 +35,9 @@
defines_verify = true
formal_verify = true
translate_off_verify = true
+
+.PHONY: systemverilog_tests_clean
+systemverilog_tests_clean:
+ @rm -rf $(foreach test,$(TESTS),$(test)/tmp)
+
+clean: systemverilog_tests_clean
diff --git a/systemverilog-plugin/tests/break_continue/break_continue.tcl b/systemverilog-plugin/tests/break_continue/break_continue.tcl
index 911db18..d496367 100644
--- a/systemverilog-plugin/tests/break_continue/break_continue.tcl
+++ b/systemverilog-plugin/tests/break_continue/break_continue.tcl
@@ -2,12 +2,10 @@
if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
yosys -import ;# ingest plugin commands
-set TMP_DIR /tmp
-if { [info exists ::env(TMPDIR) ] } {
- set TMP_DIR $::env(TMPDIR)
-}
+set TMP_DIR $::env(TEST_OUTPUT_PREFIX)/tmp
+file mkdir $TMP_DIR
# Testing simple round-trip
-read_systemverilog -o $TMP_DIR/break-continue-test $::env(DESIGN_TOP).v
+read_systemverilog -o $TMP_DIR $::env(DESIGN_TOP).v
prep
write_table [test_output_path $::env(DESIGN_TOP).out]
diff --git a/systemverilog-plugin/tests/counter/counter.tcl b/systemverilog-plugin/tests/counter/counter.tcl
index 56c9c03..28a4447 100644
--- a/systemverilog-plugin/tests/counter/counter.tcl
+++ b/systemverilog-plugin/tests/counter/counter.tcl
@@ -2,11 +2,9 @@
if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
yosys -import ;# ingest plugin commands
-set TMP_DIR /tmp
-if { [info exists ::env(TMPDIR) ] } {
- set TMP_DIR $::env(TMPDIR)
-}
+set TMP_DIR $::env(TEST_OUTPUT_PREFIX)/tmp
+file mkdir $TMP_DIR
# Testing simple round-trip
-read_systemverilog -o $TMP_DIR/counter-test $::env(DESIGN_TOP).v
+read_systemverilog -o $TMP_DIR $::env(DESIGN_TOP).v
write_verilog
diff --git a/systemverilog-plugin/tests/debug-flag/debug-flag.tcl b/systemverilog-plugin/tests/debug-flag/debug-flag.tcl
index 86cfee5..3b3a568 100644
--- a/systemverilog-plugin/tests/debug-flag/debug-flag.tcl
+++ b/systemverilog-plugin/tests/debug-flag/debug-flag.tcl
@@ -2,15 +2,13 @@
if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
yosys -import ;# ingest plugin commands
-set TMP_DIR /tmp
-if { [info exists ::env(TMPDIR) ] } {
- set TMP_DIR $::env(TMPDIR)
-}
+set TMP_DIR $::env(TEST_OUTPUT_PREFIX)/tmp
+file mkdir $TMP_DIR
# Testing simple round-trip
-read_systemverilog -debug -odir $TMP_DIR/debug-flag-test -defer $::env(DESIGN_TOP)-pkg.sv
-read_systemverilog -debug -odir $TMP_DIR/debug-flag-test -defer $::env(DESIGN_TOP)-buf.sv
-read_systemverilog -debug -odir $TMP_DIR/debug-flag-test -defer $::env(DESIGN_TOP).v
-read_systemverilog -debug -odir $TMP_DIR/debug-flag-test -link
+read_systemverilog -debug -odir $TMP_DIR -defer $::env(DESIGN_TOP)-pkg.sv
+read_systemverilog -debug -odir $TMP_DIR -defer $::env(DESIGN_TOP)-buf.sv
+read_systemverilog -debug -odir $TMP_DIR -defer $::env(DESIGN_TOP).v
+read_systemverilog -debug -odir $TMP_DIR -link
hierarchy
write_verilog
diff --git a/systemverilog-plugin/tests/defaults/defaults.tcl b/systemverilog-plugin/tests/defaults/defaults.tcl
index 6639834..804d2e5 100644
--- a/systemverilog-plugin/tests/defaults/defaults.tcl
+++ b/systemverilog-plugin/tests/defaults/defaults.tcl
@@ -2,22 +2,20 @@
if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
yosys -import ;# ingest plugin commands
-set TMP_DIR /tmp
-if { [info exists ::env(TMPDIR) ] } {
- set TMP_DIR $::env(TMPDIR)
-}
+set TMP_DIR $::env(TEST_OUTPUT_PREFIX)/tmp
+file mkdir $TMP_DIR
# Define forbidden value
systemverilog_defaults -add -DPAKALA
# Stash it
systemverilog_defaults -push
systemverilog_defaults -clear
-read_systemverilog -o $TMP_DIR/defaults-test $::env(DESIGN_TOP).v
+read_systemverilog -o $TMP_DIR $::env(DESIGN_TOP).v
# Allow parsing the module again
delete top
systemverilog_defaults -pop
# Skip check for forbidden value
systemverilog_defaults -add -Pbypass=1
-read_systemverilog -o $TMP_DIR/defaults-test $::env(DESIGN_TOP).v
+read_systemverilog -o $TMP_DIR $::env(DESIGN_TOP).v
hierarchy
write_verilog
diff --git a/systemverilog-plugin/tests/defines/defines.tcl b/systemverilog-plugin/tests/defines/defines.tcl
index 81a93d4..14b37ad 100644
--- a/systemverilog-plugin/tests/defines/defines.tcl
+++ b/systemverilog-plugin/tests/defines/defines.tcl
@@ -2,14 +2,12 @@
if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
yosys -import ;# ingest plugin commands
-set TMP_DIR /tmp
-if { [info exists ::env(TMPDIR) ] } {
- set TMP_DIR $::env(TMPDIR)
-}
+set TMP_DIR $::env(TEST_OUTPUT_PREFIX)/tmp
+file mkdir $TMP_DIR
systemverilog_defines -DPONA
systemverilog_defines -DPAKALA
systemverilog_defines -UPAKALA
-read_systemverilog -o $TMP_DIR/defines-test $::env(DESIGN_TOP).v
+read_systemverilog -o $TMP_DIR $::env(DESIGN_TOP).v
hierarchy
write_verilog
diff --git a/systemverilog-plugin/tests/formal/formal.tcl b/systemverilog-plugin/tests/formal/formal.tcl
index e383c08..b2590d3 100644
--- a/systemverilog-plugin/tests/formal/formal.tcl
+++ b/systemverilog-plugin/tests/formal/formal.tcl
@@ -2,11 +2,9 @@
if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
yosys -import ;# ingest plugin commands
-set TMP_DIR /tmp
-if { [info exists ::env(TMPDIR) ] } {
- set TMP_DIR $::env(TMPDIR)
-}
+set TMP_DIR $::env(TEST_OUTPUT_PREFIX)/tmp
+file mkdir $TMP_DIR
-read_systemverilog -o $TMP_DIR/formal-test -formal $::env(DESIGN_TOP).v
+read_systemverilog -o $TMP_DIR -formal $::env(DESIGN_TOP).v
hierarchy
write_verilog
diff --git a/systemverilog-plugin/tests/report-flag/report-flag.tcl b/systemverilog-plugin/tests/report-flag/report-flag.tcl
index 3a3cc6d..d49a46b 100644
--- a/systemverilog-plugin/tests/report-flag/report-flag.tcl
+++ b/systemverilog-plugin/tests/report-flag/report-flag.tcl
@@ -2,15 +2,13 @@
if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
yosys -import ;# ingest plugin commands
-set TMP_DIR /tmp
-if { [info exists ::env(TMPDIR) ] } {
- set TMP_DIR $::env(TMPDIR)
-}
+set TMP_DIR $::env(TEST_OUTPUT_PREFIX)/tmp
+file mkdir $TMP_DIR
# Testing simple round-trip
-read_systemverilog -report $TMP_DIR/report-flag-test -odir $TMP_DIR/report-flag-test -defer $::env(DESIGN_TOP)-pkg.sv
-read_systemverilog -report $TMP_DIR/report-flag-test -odir $TMP_DIR/report-flag-test -defer $::env(DESIGN_TOP)-buf.sv
-read_systemverilog -report $TMP_DIR/report-flag-test -odir $TMP_DIR/report-flag-test -defer $::env(DESIGN_TOP).v
-read_systemverilog -report $TMP_DIR/report-flag-test -odir $TMP_DIR/report-flag-test -link
+read_systemverilog -report $TMP_DIR -odir $TMP_DIR -defer $::env(DESIGN_TOP)-pkg.sv
+read_systemverilog -report $TMP_DIR -odir $TMP_DIR -defer $::env(DESIGN_TOP)-buf.sv
+read_systemverilog -report $TMP_DIR -odir $TMP_DIR -defer $::env(DESIGN_TOP).v
+read_systemverilog -report $TMP_DIR -odir $TMP_DIR -link
hierarchy
write_verilog
diff --git a/systemverilog-plugin/tests/separate-compilation/separate-compilation.tcl b/systemverilog-plugin/tests/separate-compilation/separate-compilation.tcl
index e9eec92..46b029a 100644
--- a/systemverilog-plugin/tests/separate-compilation/separate-compilation.tcl
+++ b/systemverilog-plugin/tests/separate-compilation/separate-compilation.tcl
@@ -2,15 +2,13 @@
if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
yosys -import ;# ingest plugin commands
-set TMP_DIR /tmp
-if { [info exists ::env(TMPDIR) ] } {
- set TMP_DIR $::env(TMPDIR)
-}
+set TMP_DIR $::env(TEST_OUTPUT_PREFIX)/tmp
+file mkdir $TMP_DIR
# Testing simple round-trip
-read_systemverilog -odir $TMP_DIR/separate-compilation-test -defer $::env(DESIGN_TOP)-pkg.sv
-read_systemverilog -odir $TMP_DIR/separate-compilation-test -defer $::env(DESIGN_TOP)-buf.sv
-read_systemverilog -odir $TMP_DIR/separate-compilation-test -defer $::env(DESIGN_TOP).v
-read_systemverilog -odir $TMP_DIR/separate-compilation-test -link
+read_systemverilog -odir $TMP_DIR -defer $::env(DESIGN_TOP)-pkg.sv
+read_systemverilog -odir $TMP_DIR -defer $::env(DESIGN_TOP)-buf.sv
+read_systemverilog -odir $TMP_DIR -defer $::env(DESIGN_TOP).v
+read_systemverilog -odir $TMP_DIR -link
hierarchy
write_verilog
diff --git a/systemverilog-plugin/tests/translate_off/translate_off.tcl b/systemverilog-plugin/tests/translate_off/translate_off.tcl
index d7e0478..d836d1e 100644
--- a/systemverilog-plugin/tests/translate_off/translate_off.tcl
+++ b/systemverilog-plugin/tests/translate_off/translate_off.tcl
@@ -2,9 +2,7 @@
if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
yosys -import ;# ingest plugin commands
-set TMP_DIR /tmp
-if { [info exists ::env(TMPDIR) ] } {
- set TMP_DIR $::env(TMPDIR)
-}
+set TMP_DIR $::env(TEST_OUTPUT_PREFIX)/tmp
+file mkdir $TMP_DIR
-read_systemverilog -o $TMP_DIR/translate_off-test $::env(DESIGN_TOP).v
+read_systemverilog -o $TMP_DIR $::env(DESIGN_TOP).v
