SDC: Check waveform values when adding clock
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
diff --git a/sdc-plugin/clocks.cc b/sdc-plugin/clocks.cc
index 3854108..9fa811e 100644
--- a/sdc-plugin/clocks.cc
+++ b/sdc-plugin/clocks.cc
@@ -39,6 +39,9 @@
} else {
log("Inserting clock %s with period %f, r:%f, f:%f\n", name.c_str(),
period, rising_edge, falling_edge);
+ if (falling_edge > period) {
+ log_error("Phase shift on clock %s exceeds 360 degrees\nRising edge: %f, Falling edge: %f, Clock period:%f\n", name.c_str(), rising_edge, falling_edge, period);
+ }
clocks_.emplace_back(name, wire, period, rising_edge, falling_edge);
}
}
@@ -223,14 +226,15 @@
void Clock::UpdateWaveform(float rising_edge, float falling_edge) {
rising_edge_ = rising_edge;
falling_edge_ = falling_edge;
+ if (falling_edge_ > period_) {
+ log_error("Phase shift on clock %s exceeds 360 degrees\nRising edge: %f, Falling edge: %f, Clock period:%f\n", name_.c_str(), rising_edge_, falling_edge_, period_);
+ }
}
void Clock::ApplyShift(float rising_edge) {
- rising_edge_ += rising_edge;
- falling_edge_ += rising_edge;
- if (falling_edge_ > period_) {
- log_error("Phase shift exceeds 360 degrees\n");
- }
+ float new_rising_edge = rising_edge_ + rising_edge;
+ float new_falling_edge = falling_edge_ + rising_edge;
+ UpdateWaveform(new_rising_edge, new_falling_edge);
}
std::string Clock::ClockWireName(RTLIL::Wire* wire) {
diff --git a/sdc-plugin/tests/pll/pll.golden.sdc b/sdc-plugin/tests/pll/pll.golden.sdc
index 4080fa4..8f82a93 100644
--- a/sdc-plugin/tests/pll/pll.golden.sdc
+++ b/sdc-plugin/tests/pll/pll.golden.sdc
@@ -2,5 +2,5 @@
create_clock -period 10 -waveform {1 6} \$techmap1716\FDCE_0.C
create_clock -period 10 -waveform {3.5 8.5} \$auto\$clkbufmap.cc:247:execute\$1829
create_clock -period 10 -waveform {4.5 9.5} main_clkout0
-create_clock -period 2.5 -waveform {1 2.25} \$auto\$clkbufmap.cc:247:execute\$1831
-create_clock -period 2.5 -waveform {2 3.25} main_clkout1
+create_clock -period 5 -waveform {1 3.5} \$auto\$clkbufmap.cc:247:execute\$1831
+create_clock -period 5 -waveform {2 4.5} main_clkout1
diff --git a/sdc-plugin/tests/pll/pll.v b/sdc-plugin/tests/pll/pll.v
index 17a0064..64b9750 100644
--- a/sdc-plugin/tests/pll/pll.v
+++ b/sdc-plugin/tests/pll/pll.v
@@ -31,7 +31,7 @@
.CLKIN1_PERIOD(10.0),
.CLKOUT0_DIVIDE(4'd12),
.CLKOUT0_PHASE(90.0),
- .CLKOUT1_DIVIDE(2'd3),
+ .CLKOUT1_DIVIDE(3'd6),
.CLKOUT1_PHASE(0.0),
.DIVCLK_DIVIDE(1'd1),
.REF_JITTER1(0.01),
