SDC: Clang format Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>

diff --git a/sdc-plugin/buffers.cc b/sdc-plugin/buffers.cc
index 125b549..eb4d0a7 100644
--- a/sdc-plugin/buffers.cc
+++ b/sdc-plugin/buffers.cc

@@ -18,6 +18,7 @@
 #include "buffers.h"
 
 const std::vector<std::string> Pll::inputs = {"CLKIN1", "CLKIN2"};
-const std::vector<std::string> Pll::outputs = {"CLKOUT0", "CLKOUT1", "CLKOUT2", "CLKOUT3", "CLKOUT4", "CLKOUT5"};
+const std::vector<std::string> Pll::outputs = {"CLKOUT0", "CLKOUT1", "CLKOUT2",
+                                               "CLKOUT3", "CLKOUT4", "CLKOUT5"};
 const float Pll::delay = 0;
 const std::string Pll::name = "PLLE2_ADV";

diff --git a/sdc-plugin/clocks.cc b/sdc-plugin/clocks.cc
index 09acff7..4a99e37 100644
--- a/sdc-plugin/clocks.cc
+++ b/sdc-plugin/clocks.cc

@@ -35,7 +35,8 @@
 	log("Clock %s already exists and will be overwritten\n", name.c_str());
 	clock->UpdateClock(wire, period, rising_edge, falling_edge);
     } else {
-	log("Inserting clock %s with period %f, r:%f, f:%f\n", name.c_str(), period, rising_edge, falling_edge);
+	log("Inserting clock %s with period %f, r:%f, f:%f\n", name.c_str(),
+	    period, rising_edge, falling_edge);
 	clocks_.emplace_back(name, wire, period, rising_edge, falling_edge);
     }
 }
@@ -150,8 +151,8 @@
 #ifdef SDC_DEBUG
 	log("Clock wire %s\n", RTLIL::unescape_id(clock_wire->name).c_str());
 #endif
-	auto buf_wires = pass->FindSinkWiresForCellType(
-	    clock_wire, buffer.name, buffer.output);
+	auto buf_wires = pass->FindSinkWiresForCellType(clock_wire, buffer.name,
+	                                                buffer.output);
 	int path_delay(0);
 	for (auto wire : buf_wires) {
 #ifdef SDC_DEBUG
@@ -170,7 +171,8 @@
     for (auto& clock : clocks_) {
 	auto clock_wires = clock.GetClockWires();
 	file << "create_clock -period " << clock.Period();
-	file << " -waveform {" << clock.RisingEdge() << " " << clock.FallingEdge() << "}";
+	file << " -waveform {" << clock.RisingEdge() << " "
+	     << clock.FallingEdge() << "}";
 	file << " " << Clock::ClockWireName(clock_wires.at(0));
 	file << std::endl;
     }
@@ -202,14 +204,16 @@
     }
 }
 
-void Clock::UpdateClock(RTLIL::Wire* wire, float period, float rising_edge, float falling_edge) {
+void Clock::UpdateClock(RTLIL::Wire* wire, float period, float rising_edge,
+                        float falling_edge) {
     UpdateWires(wire);
     UpdatePeriod(period);
     UpdateWaveform(rising_edge, falling_edge);
 }
 
 void Clock::UpdateWires(RTLIL::Wire* wire) {
-    if (std::find(clock_wires_.begin(), clock_wires_.end(), wire) == clock_wires_.end()) {
+    if (std::find(clock_wires_.begin(), clock_wires_.end(), wire) ==
+        clock_wires_.end()) {
 	clock_wires_.push_back(wire);
     }
 }

diff --git a/sdc-plugin/clocks.h b/sdc-plugin/clocks.h
index c1147a0..df60b6d 100644
--- a/sdc-plugin/clocks.h
+++ b/sdc-plugin/clocks.h

@@ -33,15 +33,16 @@
    public:
     Clock(const std::string& name, RTLIL::Wire* wire, float period,
           float rising_edge, float falling_edge);
-    Clock(const std::string& name, std::vector<RTLIL::Wire*> wires, float period,
-          float rising_edge, float falling_edge);
+    Clock(const std::string& name, std::vector<RTLIL::Wire*> wires,
+          float period, float rising_edge, float falling_edge);
     void AddWire(RTLIL::Wire* wire);
     std::vector<RTLIL::Wire*> GetClockWires() { return clock_wires_; }
     const std::string& Name() const { return name_; }
     float Period() { return period_; }
     float RisingEdge() { return rising_edge_; }
     float FallingEdge() { return falling_edge_; }
-    void UpdateClock(RTLIL::Wire* wire, float period, float rising_edge, float falling_edge);
+    void UpdateClock(RTLIL::Wire* wire, float period, float rising_edge,
+                     float falling_edge);
     static std::string ClockWireName(RTLIL::Wire* wire);
 
    private:
@@ -58,15 +59,13 @@
 
 class Clocks {
    public:
-    void AddClock(const std::string& name,
-                  std::vector<RTLIL::Wire*> wires, float period,
-                  float rising_edge, float falling_edge);
+    void AddClock(const std::string& name, std::vector<RTLIL::Wire*> wires,
+                  float period, float rising_edge, float falling_edge);
     void AddClock(const std::string& name, RTLIL::Wire* wire, float period,
                   float rising_edge, float falling_edge);
     void AddClock(Clock& clock);
-    void AddClockWires(const std::string& name,
-                       std::vector<RTLIL::Wire*> wires, float period,
-                       float rising_edge, float falling_edge);
+    void AddClockWires(const std::string& name, std::vector<RTLIL::Wire*> wires,
+                       float period, float rising_edge, float falling_edge);
     void AddClockWire(const std::string& name, RTLIL::Wire* wire, float period,
                       float rising_edge, float falling_edge);
     std::vector<std::string> GetClockNames();
@@ -77,7 +76,8 @@
 
    private:
     std::vector<Clock> clocks_;
-    void PropagateThroughBuffer(BufferPropagation* pass, Clock& clock, Buffer buffer);
+    void PropagateThroughBuffer(BufferPropagation* pass, Clock& clock,
+                                Buffer buffer);
 };
 
 #endif  // _CLOCKS_H_

diff --git a/sdc-plugin/propagation.h b/sdc-plugin/propagation.h
index e09fc84..1f3125c 100644
--- a/sdc-plugin/propagation.h
+++ b/sdc-plugin/propagation.h

@@ -65,7 +65,7 @@
         : Propagation(design, pass) {}
 
     void Run(Clocks& clocks) override { clocks.Propagate(this); }
-    std::vector<Clock> FindSinkClocksForCellType(
-        RTLIL::Wire* driver_wire, const std::string& cell_type);
+    std::vector<Clock> FindSinkClocksForCellType(RTLIL::Wire* driver_wire,
+                                                 const std::string& cell_type);
 };
 #endif  // PROPAGATION_H_