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foss-fpga-tools/yosys-symbiflow-plugins/474724189715dd0d4fbb51d2f1cb2fa22f205722^1..474724189715dd0d4fbb51d2f1cb2fa22f205722/.
commit
474724189715dd0d4fbb51d2f1cb2fa22f205722
[log]
author
Mariusz Glebocki <mglebocki@antmicro.com>
Tue May 16 17:36:23 2023 +0200
committer
GitHub <noreply@github.com>
Tue May 16 17:36:23 2023 +0200
tree
a5e058408ad00c10e4743ea7d6e7e4b0137f044b
parent
2ec0e35c3ff9c2a2379ce5c802af52bd556f8d09 [diff]
parent
62c6550f86ddf1ac3c6100c4f7b8dc6e80042797 [diff]
Merge pull request #514 from antmicro/mglb/FixTests

systemverilog-plugin: Remove temporary test files.
diff --git a/systemverilog-plugin/tests/Makefile b/systemverilog-plugin/tests/Makefile
index 94f6563..dcdbafd 100644
--- a/systemverilog-plugin/tests/Makefile
+++ b/systemverilog-plugin/tests/Makefile

@@ -35,3 +35,9 @@
 defines_verify = true
 formal_verify = true
 translate_off_verify = true
+
+.PHONY: systemverilog_tests_clean
+systemverilog_tests_clean:
+	@rm -rf $(foreach test,$(TESTS),$(test)/tmp)
+
+clean: systemverilog_tests_clean

diff --git a/systemverilog-plugin/tests/break_continue/break_continue.tcl b/systemverilog-plugin/tests/break_continue/break_continue.tcl
index 911db18..ce1b4cf 100644
--- a/systemverilog-plugin/tests/break_continue/break_continue.tcl
+++ b/systemverilog-plugin/tests/break_continue/break_continue.tcl

@@ -2,12 +2,10 @@
 if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
 yosys -import  ;# ingest plugin commands
 
-set TMP_DIR /tmp
-if { [info exists ::env(TMPDIR) ] } {
-  set TMP_DIR $::env(TMPDIR)
-}
+set TMP_DIR ::env(TEST_OUTPUT_PREFIX)/tmp
+file mkdir $TMP_DIR
 
 # Testing simple round-trip
-read_systemverilog -o $TMP_DIR/break-continue-test $::env(DESIGN_TOP).v
+read_systemverilog -o $TMP_DIR $::env(DESIGN_TOP).v
 prep
 write_table [test_output_path $::env(DESIGN_TOP).out]

diff --git a/systemverilog-plugin/tests/counter/counter.tcl b/systemverilog-plugin/tests/counter/counter.tcl
index 56c9c03..1904a4b 100644
--- a/systemverilog-plugin/tests/counter/counter.tcl
+++ b/systemverilog-plugin/tests/counter/counter.tcl

@@ -2,11 +2,9 @@
 if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
 yosys -import  ;# ingest plugin commands
 
-set TMP_DIR /tmp
-if { [info exists ::env(TMPDIR) ] } {
-  set TMP_DIR $::env(TMPDIR)
-}
+set TMP_DIR ::env(TEST_OUTPUT_PREFIX)/tmp
+file mkdir $TMP_DIR
 
 # Testing simple round-trip
-read_systemverilog -o $TMP_DIR/counter-test $::env(DESIGN_TOP).v
+read_systemverilog -o $TMP_DIR $::env(DESIGN_TOP).v
 write_verilog

diff --git a/systemverilog-plugin/tests/debug-flag/debug-flag.tcl b/systemverilog-plugin/tests/debug-flag/debug-flag.tcl
index 86cfee5..17b84db 100644
--- a/systemverilog-plugin/tests/debug-flag/debug-flag.tcl
+++ b/systemverilog-plugin/tests/debug-flag/debug-flag.tcl

@@ -2,15 +2,13 @@
 if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
 yosys -import  ;# ingest plugin commands
 
-set TMP_DIR /tmp
-if { [info exists ::env(TMPDIR) ] } {
-  set TMP_DIR $::env(TMPDIR)
-}
+set TMP_DIR ::env(TEST_OUTPUT_PREFIX)/tmp
+file mkdir $TMP_DIR
 
 # Testing simple round-trip
-read_systemverilog -debug -odir $TMP_DIR/debug-flag-test -defer $::env(DESIGN_TOP)-pkg.sv
-read_systemverilog -debug -odir $TMP_DIR/debug-flag-test -defer $::env(DESIGN_TOP)-buf.sv
-read_systemverilog -debug -odir $TMP_DIR/debug-flag-test -defer $::env(DESIGN_TOP).v
-read_systemverilog -debug -odir $TMP_DIR/debug-flag-test -link
+read_systemverilog -debug -odir $TMP_DIR -defer $::env(DESIGN_TOP)-pkg.sv
+read_systemverilog -debug -odir $TMP_DIR -defer $::env(DESIGN_TOP)-buf.sv
+read_systemverilog -debug -odir $TMP_DIR -defer $::env(DESIGN_TOP).v
+read_systemverilog -debug -odir $TMP_DIR -link
 hierarchy
 write_verilog

diff --git a/systemverilog-plugin/tests/defaults/defaults.tcl b/systemverilog-plugin/tests/defaults/defaults.tcl
index 6639834..14750d7 100644
--- a/systemverilog-plugin/tests/defaults/defaults.tcl
+++ b/systemverilog-plugin/tests/defaults/defaults.tcl

@@ -2,22 +2,20 @@
 if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
 yosys -import  ;# ingest plugin commands
 
-set TMP_DIR /tmp
-if { [info exists ::env(TMPDIR) ] } {
-  set TMP_DIR $::env(TMPDIR)
-}
+set TMP_DIR ::env(TEST_OUTPUT_PREFIX)/tmp
+file mkdir $TMP_DIR
 
 # Define forbidden value
 systemverilog_defaults -add -DPAKALA
 # Stash it
 systemverilog_defaults -push
 systemverilog_defaults -clear
-read_systemverilog -o $TMP_DIR/defaults-test $::env(DESIGN_TOP).v
+read_systemverilog -o $TMP_DIR $::env(DESIGN_TOP).v
 # Allow parsing the module again
 delete top
 systemverilog_defaults -pop
 # Skip check for forbidden value
 systemverilog_defaults -add -Pbypass=1
-read_systemverilog -o $TMP_DIR/defaults-test $::env(DESIGN_TOP).v
+read_systemverilog -o $TMP_DIR $::env(DESIGN_TOP).v
 hierarchy
 write_verilog

diff --git a/systemverilog-plugin/tests/defines/defines.tcl b/systemverilog-plugin/tests/defines/defines.tcl
index 81a93d4..f1ccc67 100644
--- a/systemverilog-plugin/tests/defines/defines.tcl
+++ b/systemverilog-plugin/tests/defines/defines.tcl

@@ -2,14 +2,12 @@
 if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
 yosys -import  ;# ingest plugin commands
 
-set TMP_DIR /tmp
-if { [info exists ::env(TMPDIR) ] } {
-  set TMP_DIR $::env(TMPDIR)
-}
+set TMP_DIR ::env(TEST_OUTPUT_PREFIX)/tmp
+file mkdir $TMP_DIR
 
 systemverilog_defines -DPONA
 systemverilog_defines -DPAKALA
 systemverilog_defines -UPAKALA
-read_systemverilog -o $TMP_DIR/defines-test $::env(DESIGN_TOP).v
+read_systemverilog -o $TMP_DIR $::env(DESIGN_TOP).v
 hierarchy
 write_verilog

diff --git a/systemverilog-plugin/tests/formal/formal.tcl b/systemverilog-plugin/tests/formal/formal.tcl
index e383c08..2eba6ac 100644
--- a/systemverilog-plugin/tests/formal/formal.tcl
+++ b/systemverilog-plugin/tests/formal/formal.tcl

@@ -2,11 +2,9 @@
 if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
 yosys -import  ;# ingest plugin commands
 
-set TMP_DIR /tmp
-if { [info exists ::env(TMPDIR) ] } {
-  set TMP_DIR $::env(TMPDIR)
-}
+set TMP_DIR ::env(TEST_OUTPUT_PREFIX)/tmp
+file mkdir $TMP_DIR
 
-read_systemverilog -o $TMP_DIR/formal-test -formal $::env(DESIGN_TOP).v
+read_systemverilog -o $TMP_DIR -formal $::env(DESIGN_TOP).v
 hierarchy
 write_verilog

diff --git a/systemverilog-plugin/tests/report-flag/report-flag.tcl b/systemverilog-plugin/tests/report-flag/report-flag.tcl
index 3a3cc6d..df1b087 100644
--- a/systemverilog-plugin/tests/report-flag/report-flag.tcl
+++ b/systemverilog-plugin/tests/report-flag/report-flag.tcl

@@ -2,15 +2,13 @@
 if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
 yosys -import  ;# ingest plugin commands
 
-set TMP_DIR /tmp
-if { [info exists ::env(TMPDIR) ] } {
-  set TMP_DIR $::env(TMPDIR)
-}
+set TMP_DIR ::env(TEST_OUTPUT_PREFIX)/tmp
+file mkdir $TMP_DIR
 
 # Testing simple round-trip
-read_systemverilog -report $TMP_DIR/report-flag-test -odir $TMP_DIR/report-flag-test -defer $::env(DESIGN_TOP)-pkg.sv
-read_systemverilog -report $TMP_DIR/report-flag-test -odir $TMP_DIR/report-flag-test -defer $::env(DESIGN_TOP)-buf.sv
-read_systemverilog -report $TMP_DIR/report-flag-test -odir $TMP_DIR/report-flag-test -defer $::env(DESIGN_TOP).v
-read_systemverilog -report $TMP_DIR/report-flag-test -odir $TMP_DIR/report-flag-test -link
+read_systemverilog -report $TMP_DIR -odir $TMP_DIR -defer $::env(DESIGN_TOP)-pkg.sv
+read_systemverilog -report $TMP_DIR -odir $TMP_DIR -defer $::env(DESIGN_TOP)-buf.sv
+read_systemverilog -report $TMP_DIR -odir $TMP_DIR -defer $::env(DESIGN_TOP).v
+read_systemverilog -report $TMP_DIR -odir $TMP_DIR -link
 hierarchy
 write_verilog

diff --git a/systemverilog-plugin/tests/separate-compilation/separate-compilation.tcl b/systemverilog-plugin/tests/separate-compilation/separate-compilation.tcl
index e9eec92..82cbfc9 100644
--- a/systemverilog-plugin/tests/separate-compilation/separate-compilation.tcl
+++ b/systemverilog-plugin/tests/separate-compilation/separate-compilation.tcl

@@ -2,15 +2,13 @@
 if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
 yosys -import  ;# ingest plugin commands
 
-set TMP_DIR /tmp
-if { [info exists ::env(TMPDIR) ] } {
-  set TMP_DIR $::env(TMPDIR)
-}
+set TMP_DIR ::env(TEST_OUTPUT_PREFIX)/tmp
+file mkdir $TMP_DIR
 
 # Testing simple round-trip
-read_systemverilog -odir $TMP_DIR/separate-compilation-test -defer $::env(DESIGN_TOP)-pkg.sv
-read_systemverilog -odir $TMP_DIR/separate-compilation-test -defer $::env(DESIGN_TOP)-buf.sv
-read_systemverilog -odir $TMP_DIR/separate-compilation-test -defer $::env(DESIGN_TOP).v
-read_systemverilog -odir $TMP_DIR/separate-compilation-test -link
+read_systemverilog -odir $TMP_DIR -defer $::env(DESIGN_TOP)-pkg.sv
+read_systemverilog -odir $TMP_DIR -defer $::env(DESIGN_TOP)-buf.sv
+read_systemverilog -odir $TMP_DIR -defer $::env(DESIGN_TOP).v
+read_systemverilog -odir $TMP_DIR -link
 hierarchy
 write_verilog

diff --git a/systemverilog-plugin/tests/translate_off/translate_off.tcl b/systemverilog-plugin/tests/translate_off/translate_off.tcl
index d7e0478..15e411b 100644
--- a/systemverilog-plugin/tests/translate_off/translate_off.tcl
+++ b/systemverilog-plugin/tests/translate_off/translate_off.tcl

@@ -2,9 +2,7 @@
 if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
 yosys -import  ;# ingest plugin commands
 
-set TMP_DIR /tmp
-if { [info exists ::env(TMPDIR) ] } {
-  set TMP_DIR $::env(TMPDIR)
-}
+set TMP_DIR ::env(TEST_OUTPUT_PREFIX)/tmp
+file mkdir $TMP_DIR
 
-read_systemverilog -o $TMP_DIR/translate_off-test $::env(DESIGN_TOP).v
+read_systemverilog -o $TMP_DIR $::env(DESIGN_TOP).v