Force -parse flag for Surelog when reading Verilog directly

Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>

uhdm-plugin/uhdmsurelogastfrontend.cc

diff --git a/uhdm-plugin/uhdmsurelogastfrontend.cc b/uhdm-plugin/uhdmsurelogastfrontend.cc
index ce79772..24bcbb1 100644
--- a/uhdm-plugin/uhdmsurelogastfrontend.cc
+++ b/uhdm-plugin/uhdmsurelogastfrontend.cc
@@ -110,6 +110,12 @@
         if (!success) {
             log_error("Error parsing Surelog arguments!\n");
         }
+        // Force -parse flag settings even if it wasn't specified
+        clp->setwritePpOutput(true);
+        clp->setParse(true);
+        clp->setCompile(true);
+        clp->setElaborate(true);
+
         SURELOG::scompiler *compiler = nullptr;
         const std::vector<vpiHandle> uhdm_design = executeCompilation(symbolTable, errors, clp, compiler);