Fixed ql-iob plugin tests so they do not require the synth_quicklogic command. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

diff --git a/ql-iob-plugin/ql-iob.cc b/ql-iob-plugin/ql-iob.cc
index 47d04a9..351759c 100644
--- a/ql-iob-plugin/ql-iob.cc
+++ b/ql-iob-plugin/ql-iob.cc

@@ -27,8 +27,8 @@
 #include <regex>
 #include <sstream>
 
-#ifndef YOSYS_OVERRIDE
-#define YOSYS_OVERRIDE override
+#ifndef YS_OVERRIDE
+#define YS_OVERRIDE override
 #endif
 
 USING_YOSYS_NAMESPACE

diff --git a/ql-iob-plugin/tests/Makefile b/ql-iob-plugin/tests/Makefile
index 11a3704..ed853e1 100644
--- a/ql-iob-plugin/tests/Makefile
+++ b/ql-iob-plugin/tests/Makefile

@@ -1,6 +1,6 @@
 TESTS = sdiomux ckpad
 
-all: $(addsuffix /ok,$(TESTS))
+all: clean $(addsuffix /ok,$(TESTS))
 
 clean:
 	@find . -name "ok" | xargs rm -rf

diff --git a/ql-iob-plugin/tests/ckpad/script.ys b/ql-iob-plugin/tests/ckpad/script.ys
index fad6921..fa37835 100644
--- a/ql-iob-plugin/tests/ckpad/script.ys
+++ b/ql-iob-plugin/tests/ckpad/script.ys

@@ -1,7 +1,18 @@
 plugin -i ../../ql-iob.so
 read_verilog design.v
 
-synth_quicklogic 
+# Generic synthesis
+synth -lut 4 -flatten -auto-top
+
+# Techmap
+read_verilog -lib ../common/pp3_cells_sim.v
+techmap -map ../common/pp3_cells_map.v
+
+# Insert QuickLogic specific IOBs and clock buffers
+clkbufmap -buf $_BUF_ Y:A -inpad ckpad Q:P
+iopadmap -bits -outpad outpad A:P -inpad inpad Q:P -tinoutpad bipad EN:Q:A:P A:top
+opt_clean
+
 stat
 
 quicklogic_iob design.pcf ../pinmap.csv

diff --git a/ql-iob-plugin/tests/common/pp3_cells_map.v b/ql-iob-plugin/tests/common/pp3_cells_map.v
new file mode 100644
index 0000000..c68042e
--- /dev/null
+++ b/ql-iob-plugin/tests/common/pp3_cells_map.v

@@ -0,0 +1,7 @@
+module \$_DFF_P_ (D, Q, C);
+    input D;
+    input C;
+    output Q;
+    dff _TECHMAP_REPLACE_ (.Q(Q), .D(D), .CLK(C));
+endmodule
+

diff --git a/ql-iob-plugin/tests/common/pp3_cells_sim.v b/ql-iob-plugin/tests/common/pp3_cells_sim.v
new file mode 100644
index 0000000..f77ea11
--- /dev/null
+++ b/ql-iob-plugin/tests/common/pp3_cells_sim.v

@@ -0,0 +1,48 @@
+module inpad(
+    output Q,
+    (* iopad_external_pin *)
+    input P
+);
+    assign Q = P;
+endmodule
+
+module outpad(
+    (* iopad_external_pin *)
+    output P,
+    input A
+);
+    assign P = A;
+endmodule
+
+module ckpad(
+    output Q,
+    (* iopad_external_pin *)
+    input P
+);
+    assign Q = P;
+endmodule
+
+module bipad(
+    input A,
+    input EN,
+    output Q,
+    (* iopad_external_pin *)
+    inout P
+);
+    assign Q = P;
+    assign P = EN ? A : 1'bz;
+endmodule
+
+
+module dff(
+    output reg Q,
+    input D,
+    (* clkbuf_sink *)
+    input CLK
+);
+    parameter [0:0] INIT = 1'b0;
+    initial Q = INIT;
+    always @(posedge CLK)
+        Q <= D;
+endmodule
+

diff --git a/ql-iob-plugin/tests/sdiomux/script.ys b/ql-iob-plugin/tests/sdiomux/script.ys
index 57eb53b..34587cc 100644
--- a/ql-iob-plugin/tests/sdiomux/script.ys
+++ b/ql-iob-plugin/tests/sdiomux/script.ys

@@ -1,7 +1,18 @@
 plugin -i ../../ql-iob.so
 read_verilog design.v
 
-synth_quicklogic 
+# Generic synthesis
+synth -lut 4 -flatten -auto-top
+
+# Techmap
+read_verilog -lib ../common/pp3_cells_sim.v
+techmap -map ../common/pp3_cells_map.v
+
+# Insert QuickLogic specific IOBs and clock buffers
+clkbufmap -buf $_BUF_ Y:A -inpad ckpad Q:P
+iopadmap -bits -outpad outpad A:P -inpad inpad Q:P -tinoutpad bipad EN:Q:A:P A:top
+opt_clean
+
 stat
 
 quicklogic_iob design.pcf ../pinmap.csv