| commit | 53d43e2f17daff2777241c0ecfb426c6ca8b69f3 | [log] [tgz] |
|---|---|---|
| author | Henner Zeller <h.zeller@acm.org> | Wed Mar 17 15:50:52 2021 -0700 |
| committer | Henner Zeller <h.zeller@acm.org> | Wed Mar 17 15:51:18 2021 -0700 |
| tree | 800b9390f8e5bea16669facb2466fee7e39fcb17 | |
| parent | 2772ee7bc7f939731c314e0a9837597fa8bdcb4f [diff] |
Initial run of verilog formatting. Signed-off-by: Henner Zeller <h.zeller@acm.org>
This repository contains plugins for Yosys developed as part of the SymbiFlow project.
Adds several commands that allow for collecting information about cells, nets, pins and ports in the design or a selection of objects. Additionally provides functions to convert selection on TCL lists.
Following commands are added with the plugin:
Writes out the design's fasm features based on the parameter annotations on a design cell.
The plugin adds the following command:
Implements a pass that integrates inverters into cells that have ports with the ‘invertible_pin’ attribute set.
The plugin adds the following command:
Reads the specified parameter on a selected object.
The plugin adds the following command:
QL IOB plugin annotates IO buffer cells with information from IO placement constraints.
The plugin adds the following command:
Reads Standard Delay Format (SDC) constraints, propagates these constraints across the design and writes out the complete SDC information.
The plugin adds the following commands:
Reads Xilinx Design Constraints (XDC) files and annotates the specified cells parameters with properties such as:
The plugin adds the following commands: