readme: remove redundant ToC; style

Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>

README.md

diff --git a/README.md b/README.md
index 88164e0..ad1cce8 100644
--- a/README.md
+++ b/README.md
@@ -2,26 +2,14 @@
 
 This repository contains plugins for [Yosys](https://github.com/YosysHQ/yosys.git) developed as [part of the F4PGA project](https://f4pga.org).
 
-## List of plugins
+## Design introspection plugin
 
-1. [Design introspection](#design-introspection-plugin)
-2. [FASM](#fasm-plugin)
-3. [Integrate inverters](#integrate-inverters-plugin)
-4. [Parameters](#parameters-plugin)
-5. [QuickLogic IOBs](#quicklogic-iob-plugin)
-6. [QuickLogic QLF FPGAs](#quicklogic-qlf-plugin)
-7. [SDC](#sdc-plugin)
-8. [XDC](#xdc-plugin)
-9. [SystemVerilog](#systemverilog-plugin)
-
-## Summary
-
-### Design introspection plugin
-
-Adds several commands that allow for collecting information about cells, nets, pins and ports in the design or a selection of objects.
+Adds several commands that allow for collecting information about cells, nets, pins and ports in the design or a
+selection of objects.
 Additionally provides functions to convert selection on TCL lists.
 
 Following commands are added with the plugin:
+
 * get_cells
 * get_nets
 * get_pins
@@ -29,50 +17,58 @@
 * get_count
 * selection_to_tcl_list
 
-### FASM plugin
+## FASM plugin
 
 Writes out the design's [fasm features](https://fasm.readthedocs.io/en/latest/) based on the parameter annotations on a
 design cell.
 
 The plugin adds the following command:
+
 * write_fasm
 
-### Integrate inverters plugin
+## Integrate inverters plugin
 
 Implements a pass that integrates inverters into cells that have ports with the 'invertible_pin' attribute set.
 
 The plugin adds the following command:
+
 * integrateinv
 
-### Parameters plugin
+## Parameters plugin
 
 Reads the specified parameter on a selected object.
 
 The plugin adds the following command:
+
 * getparam
 
-### QuickLogic IOB plugin
+## QuickLogic IOB plugin
 
-[QuickLogic IOB plugin](./ql-iob-plugin/) annotates IO buffer cells with information from IO placement constraints. Used during synthesis for QuickLogic EOS-S3 architecture.
+[QuickLogic IOB plugin](./ql-iob-plugin/) annotates IO buffer cells with information from IO placement constraints.
+Used during synthesis for QuickLogic EOS-S3 architecture.
 
 The plugin adds the following command:
+
 * quicklogic_iob
 
-### QuickLogic QLF FPGAs plugin
+## QuickLogic QLF FPGAs plugin
 
 [QuickLogic QLF plugin](./ql-qlf-plugin) extends Yosys with synthesis support for `qlf_k4n8` and `qlf_k6n10` architectures.
 
 The plugin adds the following command:
+
 * synth_quicklogic
 * ql_dsp
 
 Detailed help on the supported command(s) can be obtained by running `help <command_name>` in Yosys.
 
-### SDC plugin
+## SDC plugin
 
-Reads Standard Delay Format (SDC) constraints, propagates these constraints across the design and writes out the complete SDC information.
+Reads Standard Delay Format (SDC) constraints, propagates these constraints across the design and writes out the
+complete SDC information.
 
 The plugin adds the following commands:
+
 * read_sdc
 * write_sdc
 * create_clock
@@ -82,9 +78,10 @@
 * set_max_delay
 * set_clock_groups
 
-### XDC plugin
+## XDC plugin
 
 Reads Xilinx Design Constraints (XDC) files and annotates the specified cells parameters with properties such as:
+
 * INTERNAL_VREF
 * IOSTANDARD
 * SLEW
@@ -94,16 +91,18 @@
 * PACKAGE_PIN
 
 The plugin adds the following commands:
+
 * read_xdc
 * get_iobanks
 * set_property
 * get_bank_tiles
 
-### SystemVerilog plugin
+## SystemVerilog plugin
 
 Reads SystemVerilog and UHDM files and processes them into yosys AST.
 
 The plugin adds the following commands:
+
 * read_systemverilog
 * read_uhdm