readme: s/SymbiFlow/F4PGA/ Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>
diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index d5615e4..e92bb22 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md
@@ -1,18 +1,16 @@ -# Contributing to Yosys SymbiFlow Plugins +# Contributing to Yosys F4PGA Plugins -There are a couple of guidelines when contributing to Yosys SymbiFlow Plugins -which are listed here. +There are a couple of guidelines when contributing to Yosys F4PGA Plugins which are listed here. ### Sending -All contributions should be sent as -[GitHub Pull requests](https://help.github.com/articles/creating-a-pull-request-from-a-fork/). +All contributions should be sent as [GitHub Pull requests](https://help.github.com/articles/creating-a-pull-request-from-a-fork/). ### License -All software (code, associated documentation, support files, etc) in the -Yosys SymbiFlow Plugins repository are licensed under the very permissive -[ISC Licence](COPYING). A copy can be found in the [`COPYING`](COPYING) file. +All software (code, associated documentation, support files, etc) in the Yosys F4PGA Plugins repository are licensed +under the very permissive [ISC Licence](COPYING). +A copy can be found in the [`COPYING`](COPYING) file. All new contributions must also be released under this license.
diff --git a/README.md b/README.md index 9ca9b69..88164e0 100644 --- a/README.md +++ b/README.md
@@ -1,10 +1,9 @@ -# Yosys SymbiFlow Plugins +# Yosys F4PGA Plugins -This repository contains plugins for -[Yosys](https://github.com/YosysHQ/yosys.git) developed as -[part of the SymbiFlow project](https://symbiflow.github.io). +This repository contains plugins for [Yosys](https://github.com/YosysHQ/yosys.git) developed as [part of the F4PGA project](https://f4pga.org). ## List of plugins + 1. [Design introspection](#design-introspection-plugin) 2. [FASM](#fasm-plugin) 3. [Integrate inverters](#integrate-inverters-plugin) @@ -32,7 +31,8 @@ ### FASM plugin -Writes out the design's [fasm features](https://symbiflow.readthedocs.io/en/latest/fasm/docs/specification.html) based on the parameter annotations on a design cell. +Writes out the design's [fasm features](https://fasm.readthedocs.io/en/latest/) based on the parameter annotations on a +design cell. The plugin adds the following command: * write_fasm @@ -91,7 +91,7 @@ * DRIVE * IN_TERM * LOC -* PACKAGE_PIN +* PACKAGE_PIN The plugin adds the following commands: * read_xdc
diff --git a/design_introspection-plugin/tests/get_cells/get_cells.tcl b/design_introspection-plugin/tests/get_cells/get_cells.tcl index 047b150..d077924 100644 --- a/design_introspection-plugin/tests/get_cells/get_cells.tcl +++ b/design_introspection-plugin/tests/get_cells/get_cells.tcl
@@ -3,7 +3,7 @@ yosys -import ;# ingest plugin commands read_verilog $::env(DESIGN_TOP).v -# Some of symbiflow expects eblifs with only one module. +# Some of F4PGA expects eblifs with only one module. synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp
diff --git a/design_introspection-plugin/tests/get_nets/get_nets.tcl b/design_introspection-plugin/tests/get_nets/get_nets.tcl index 6ef2426..5dc7ae4 100644 --- a/design_introspection-plugin/tests/get_nets/get_nets.tcl +++ b/design_introspection-plugin/tests/get_nets/get_nets.tcl
@@ -3,7 +3,7 @@ yosys -import ;# ingest plugin commands read_verilog $::env(DESIGN_TOP).v -# Some of symbiflow expects eblifs with only one module. +# Some of F4PGA expects eblifs with only one module. synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp
diff --git a/design_introspection-plugin/tests/get_pins/get_pins.tcl b/design_introspection-plugin/tests/get_pins/get_pins.tcl index d6a64fe..43ab60c 100644 --- a/design_introspection-plugin/tests/get_pins/get_pins.tcl +++ b/design_introspection-plugin/tests/get_pins/get_pins.tcl
@@ -3,7 +3,7 @@ yosys -import ;# ingest plugin commands read_verilog $::env(DESIGN_TOP).v -# Some of symbiflow expects eblifs with only one module. +# Some of F4PGA expects eblifs with only one module. synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp
diff --git a/design_introspection-plugin/tests/get_ports/get_ports.tcl b/design_introspection-plugin/tests/get_ports/get_ports.tcl index 47d8fce..7724e28 100644 --- a/design_introspection-plugin/tests/get_ports/get_ports.tcl +++ b/design_introspection-plugin/tests/get_ports/get_ports.tcl
@@ -3,7 +3,7 @@ yosys -import ;# ingest plugin commands read_verilog $::env(DESIGN_TOP).v -# Some of symbiflow expects eblifs with only one module. +# Some of F4PGA expects eblifs with only one module. synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp help get_ports
diff --git a/sdc-plugin/propagation.cc b/sdc-plugin/propagation.cc index cfee89a..02fa865 100644 --- a/sdc-plugin/propagation.cc +++ b/sdc-plugin/propagation.cc
@@ -225,7 +225,7 @@ RTLIL::Wire *wire = FindSinkWireOnPort(cell, output); // Don't add clocks on dangling wires // TODO Remove the workaround with the WireHasSinkCell check once the following issue is fixed: - // https://github.com/SymbiFlow/yosys-symbiflow-plugins/issues/59 + // https://github.com/SymbiFlow/yosys-f4pga-plugins/issues/59 if (wire && WireHasSinkCell(wire)) { float clkout_period(pll.clkout_period.at(output)); float clkout_rising_edge(pll.clkout_rising_edge.at(output));
diff --git a/sdc-plugin/tests/set_clock_groups/set_clock_groups.tcl b/sdc-plugin/tests/set_clock_groups/set_clock_groups.tcl index cefcaca..1994806 100644 --- a/sdc-plugin/tests/set_clock_groups/set_clock_groups.tcl +++ b/sdc-plugin/tests/set_clock_groups/set_clock_groups.tcl
@@ -3,7 +3,7 @@ yosys -import ;# ingest plugin commands read_verilog $::env(DESIGN_TOP).v -# Some of symbiflow expects eblifs with only one module. +# Some of F4PGA expects eblifs with only one module. synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp set_clock_groups -group clk1 clk2
diff --git a/sdc-plugin/tests/set_false_path/set_false_path.tcl b/sdc-plugin/tests/set_false_path/set_false_path.tcl index 29c0178..e755e7e 100644 --- a/sdc-plugin/tests/set_false_path/set_false_path.tcl +++ b/sdc-plugin/tests/set_false_path/set_false_path.tcl
@@ -3,7 +3,7 @@ yosys -import ;# ingest plugin commands read_verilog $::env(DESIGN_TOP).v -# Some of symbiflow expects eblifs with only one module. +# Some of F4PGA expects eblifs with only one module. synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp # -to inter_wire net
diff --git a/sdc-plugin/tests/set_max_delay/set_max_delay.tcl b/sdc-plugin/tests/set_max_delay/set_max_delay.tcl index 92d4c55..4957485 100644 --- a/sdc-plugin/tests/set_max_delay/set_max_delay.tcl +++ b/sdc-plugin/tests/set_max_delay/set_max_delay.tcl
@@ -3,7 +3,7 @@ yosys -import ;# ingest plugin commands read_verilog $::env(DESIGN_TOP).v -# Some of symbiflow expects eblifs with only one module. +# Some of F4PGA expects eblifs with only one module. synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp # -to inter_wire net
diff --git a/xdc-plugin/tests/counter-dict/counter-dict.tcl b/xdc-plugin/tests/counter-dict/counter-dict.tcl index 91d4624..b6eb5b5 100644 --- a/xdc-plugin/tests/counter-dict/counter-dict.tcl +++ b/xdc-plugin/tests/counter-dict/counter-dict.tcl
@@ -6,7 +6,7 @@ read_verilog $::env(DESIGN_TOP).v # -flatten is used to ensure that the output eblif has only one module. -# Some of symbiflow expects eblifs with only one module. +# Some of F4PGA expects eblifs with only one module. synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp #Read the design constraints
diff --git a/xdc-plugin/tests/counter/counter.tcl b/xdc-plugin/tests/counter/counter.tcl index 0a3a62b..9347071 100644 --- a/xdc-plugin/tests/counter/counter.tcl +++ b/xdc-plugin/tests/counter/counter.tcl
@@ -6,7 +6,7 @@ read_verilog $::env(DESIGN_TOP).v # -flatten is used to ensure that the output eblif has only one module. -# Some of symbiflow expects eblifs with only one module. +# Some of F4PGA expects eblifs with only one module. synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp #Read the design constraints
diff --git a/xdc-plugin/tests/io_loc_pairs/io_loc_pairs.tcl b/xdc-plugin/tests/io_loc_pairs/io_loc_pairs.tcl index 7d99d29..d7f5506 100644 --- a/xdc-plugin/tests/io_loc_pairs/io_loc_pairs.tcl +++ b/xdc-plugin/tests/io_loc_pairs/io_loc_pairs.tcl
@@ -12,7 +12,7 @@ hierarchy -check -top top # -flatten is used to ensure that the output eblif has only one module. -# Some of symbiflow expects eblifs with only one module. +# Some of F4PGA expects eblifs with only one module. synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp -run prepare:check #Read the design constraints
diff --git a/xdc-plugin/tests/minilitex_ddr_arty/minilitex_ddr_arty.tcl b/xdc-plugin/tests/minilitex_ddr_arty/minilitex_ddr_arty.tcl index 3c5fcd5..df2555c 100644 --- a/xdc-plugin/tests/minilitex_ddr_arty/minilitex_ddr_arty.tcl +++ b/xdc-plugin/tests/minilitex_ddr_arty/minilitex_ddr_arty.tcl
@@ -6,7 +6,7 @@ read_verilog $::env(DESIGN_TOP).v read_verilog [file dirname [info script]]/VexRiscv_Lite.v # -flatten is used to ensure that the output eblif has only one module. -# Some of symbiflow expects eblifs with only one module. +# Some of F4PGA expects eblifs with only one module. synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp #Read the design constraints
diff --git a/xdc-plugin/tests/non_zero_port_indexes/non_zero_port_indexes.tcl b/xdc-plugin/tests/non_zero_port_indexes/non_zero_port_indexes.tcl index 60552c2..50872c0 100644 --- a/xdc-plugin/tests/non_zero_port_indexes/non_zero_port_indexes.tcl +++ b/xdc-plugin/tests/non_zero_port_indexes/non_zero_port_indexes.tcl
@@ -11,7 +11,7 @@ hierarchy -check -top top # -flatten is used to ensure that the output eblif has only one module. -# Some of symbiflow expects eblifs with only one module. +# Some of F4PGA expects eblifs with only one module. synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp -run prepare:check #Read the design constraints
diff --git a/xdc-plugin/tests/package_pins-dict-space/package_pins-dict-space.tcl b/xdc-plugin/tests/package_pins-dict-space/package_pins-dict-space.tcl index 506097a..7625c92 100644 --- a/xdc-plugin/tests/package_pins-dict-space/package_pins-dict-space.tcl +++ b/xdc-plugin/tests/package_pins-dict-space/package_pins-dict-space.tcl
@@ -5,7 +5,7 @@ read_verilog $::env(DESIGN_TOP).v # -flatten is used to ensure that the output eblif has only one module. -# Some of symbiflow expects eblifs with only one module. +# Some of F4PGA expects eblifs with only one module. synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp #Read the design constraints
diff --git a/xdc-plugin/tests/package_pins/package_pins.tcl b/xdc-plugin/tests/package_pins/package_pins.tcl index 7f059e7..90298eb 100644 --- a/xdc-plugin/tests/package_pins/package_pins.tcl +++ b/xdc-plugin/tests/package_pins/package_pins.tcl
@@ -5,7 +5,7 @@ read_verilog $::env(DESIGN_TOP).v # -flatten is used to ensure that the output eblif has only one module. -# Some of symbiflow expects eblifs with only one module. +# Some of F4PGA expects eblifs with only one module. synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp #Read the design constraints
diff --git a/xdc-plugin/tests/port_indexes/port_indexes.tcl b/xdc-plugin/tests/port_indexes/port_indexes.tcl index 2472ffa..c2c148a 100644 --- a/xdc-plugin/tests/port_indexes/port_indexes.tcl +++ b/xdc-plugin/tests/port_indexes/port_indexes.tcl
@@ -6,7 +6,7 @@ read_verilog $::env(DESIGN_TOP).v # -flatten is used to ensure that the output eblif has only one module. -# Some of symbiflow expects eblifs with only one module. +# Some of F4PGA expects eblifs with only one module. synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp if {[info procs unknown] != ""} {