|  | yosys -import | 
|  | if { [info procs synth_quicklogic] == {} } { plugin -i ql-qlf } | 
|  | yosys -import  ;# ingest plugin commands | 
|  |  | 
|  | read_verilog $::env(DESIGN_TOP).v | 
|  | design -save read | 
|  |  | 
|  | design -load read | 
|  | synth_quicklogic -family pp3 -top top_bram_9_16 | 
|  | yosys cd top_bram_9_16 | 
|  | stat | 
|  | select -assert-count 1 t:ckpad | 
|  | select -assert-count 35 t:inpad | 
|  | select -assert-count 16 t:outpad | 
|  | select -assert-count 1 t:ram8k_2x1_cell_macro | 
|  |  | 
|  | design -load read | 
|  | synth_quicklogic -family pp3 -top top_bram_9_32 | 
|  | yosys cd top_bram_9_32 | 
|  | stat | 
|  | select -assert-count 1 t:ckpad | 
|  | select -assert-count 51 t:inpad | 
|  | select -assert-count 32 t:outpad | 
|  | select -assert-count 1 t:ram8k_2x1_cell_macro | 
|  |  | 
|  | design -load read | 
|  | synth_quicklogic -family pp3 -top top_bram_10_16 | 
|  | yosys cd top_bram_10_16 | 
|  | stat | 
|  | select -assert-count 1 t:ckpad | 
|  | select -assert-count 37 t:inpad | 
|  | select -assert-count 16 t:outpad | 
|  | select -assert-count 1 t:ram8k_2x1_cell_macro | 
|  |  | 
|  | # BRAM initialization from file using pp3_braminig pass test | 
|  | design -load read | 
|  | synth_quicklogic -family pp3 -top top_bram_init | 
|  | yosys cd top_bram_init | 
|  | stat | 
|  | select -assert-count 1 t:ckpad | 
|  | select -assert-count 39 t:inpad | 
|  | select -assert-count 18 t:outpad | 
|  | select -assert-count 1 t:ram8k_2x1_cell_macro | 
|  |  | 
|  | set INIT 8192'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000efffabcd56781234 | 
|  | select -assert-count 1 t:ram8k_2x1_cell_macro r:INIT=$INIT \%i | 
|  |  |