Updated nexus DSP rules, added more tests for registers that include control signals Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

diff --git a/dsp-ff-plugin/nexus-dsp_rules.txt b/dsp-ff-plugin/nexus-dsp_rules.txt
index 9093182..0ed8947 100644
--- a/dsp-ff-plugin/nexus-dsp_rules.txt
+++ b/dsp-ff-plugin/nexus-dsp_rules.txt

@@ -7,7 +7,7 @@
 # SPDX-License-Identifier:ISC
 
 dsp MULT9X9 MULT18X18 MULT18X36 MULT36X36
-  port A
+  port A SIGNEDA
     clk CLK 0
     rst RSTA 0
     ena CEA 1
@@ -15,7 +15,7 @@
     set REGINPUTA=REGISTER
     map GSR=GSR
   endport
-  port B
+  port B SIGNEDB
     clk CLK 0
     rst RSTB 0
     ena CEB 1
@@ -34,7 +34,7 @@
 enddsp
 
 dsp MULTPREADD9X9 MULTPREADD18X18 MULTADDSUB18X18 MULTADDSUB36X36
-  port A
+  port A SIGNEDA
     clk CLK 0
     rst RSTA 0
     ena CEA 1
@@ -42,7 +42,7 @@
     set REGINPUTA=REGISTER
     map GSR=GSR
   endport
-  port B
+  port B SIGNEDB
     clk CLK 0
     rst RSTB 0
     ena CEB 1
@@ -50,7 +50,7 @@
     set REGINPUTB=REGISTER
     map GSR=GSR
   endport
-  port C
+  port C SIGNEDC
     clk CLK 0
     rst RSTC 0
     ena CEC 1
@@ -69,7 +69,7 @@
 enddsp
 
 dsp MULTADDSUB9X9WIDE
-  port A0
+  port A0 SIGNED
     clk CLK 0
     rst RSTA0A1 0
     ena CEA0A1 1
@@ -77,7 +77,7 @@
     set REGINPUTAB0=REGISTER
     map GSR=GSR
   endport
-  port A1
+  port A1 SIGNED
     clk CLK 0
     rst RSTA0A1 0
     ena CEA0A1 1
@@ -85,7 +85,7 @@
     set REGINPUTAB1=REGISTER
     map GSR=GSR
   endport
-  port A2
+  port A2 SIGNED
     clk CLK 0
     rst RSTA2A3 0
     ena CEA2A3 1
@@ -93,7 +93,7 @@
     set REGINPUTAB2=REGISTER
     map GSR=GSR
   endport
-  port A3
+  port A3 SIGNED
     clk CLK 0
     rst RSTA2A3 0
     ena CEA2A3 1
@@ -101,7 +101,7 @@
     set REGINPUTAB3=REGISTER
     map GSR=GSR
   endport
-  port B0
+  port B0 SIGNED
     clk CLK 0
     rst RSTB0B1 0
     ena CEB0B1 1
@@ -109,7 +109,7 @@
     set REGINPUTAB0=REGISTER
     map GSR=GSR
   endport
-  port B1
+  port B1 SIGNED
     clk CLK 0
     rst RSTB0B1 0
     ena CEB0B1 1
@@ -117,7 +117,7 @@
     set REGINPUTAB1=REGISTER
     map GSR=GSR
   endport
-  port B2
+  port B2 SIGNED
     clk CLK 0
     rst RSTB2B3 0
     ena CEB2B3 1
@@ -125,7 +125,7 @@
     set REGINPUTAB2=REGISTER
     map GSR=GSR
   endport
-  port B3
+  port B3 SIGNED
     clk CLK 0
     rst RSTB2B3 0
     ena CEB2B3 1
@@ -133,7 +133,7 @@
     set REGINPUTAB3=REGISTER
     map GSR=GSR
   endport
-  port C
+  port C SIGNED
     clk CLK 0
     rst RSTC 0
     ena CEC 1

diff --git a/dsp-ff-plugin/tests/nexus_conn_conflict/nexus_conn_conflict.tcl b/dsp-ff-plugin/tests/nexus_conn_conflict/nexus_conn_conflict.tcl
index c4cee75..87486f9 100644
--- a/dsp-ff-plugin/tests/nexus_conn_conflict/nexus_conn_conflict.tcl
+++ b/dsp-ff-plugin/tests/nexus_conn_conflict/nexus_conn_conflict.tcl

@@ -46,3 +46,13 @@
 stat
 select -assert-count 1 t:MULT9X9
 select -assert-count 18 t:FD1P3IX
+
+set TOP "conflict_dsp_port"
+design -load read
+hierarchy -top ${TOP}
+synth_nexus -flatten
+techmap -map +/nexus/cells_sim.v t:VLO t:VHI %u ;# Unmap VHI and VLO
+debug dsp_ff -rules ../../nexus-dsp_rules.txt
+stat
+select -assert-count 1 t:MULT9X9
+select -assert-count 9 t:FD1P3IX

diff --git a/dsp-ff-plugin/tests/nexus_conn_conflict/nexus_conn_conflict.v b/dsp-ff-plugin/tests/nexus_conn_conflict/nexus_conn_conflict.v
index 2224690..35856d9 100644
--- a/dsp-ff-plugin/tests/nexus_conn_conflict/nexus_conn_conflict.v
+++ b/dsp-ff-plugin/tests/nexus_conn_conflict/nexus_conn_conflict.v

@@ -125,4 +125,27 @@
 
 endmodule
 
+module conflict_dsp_port (
+    input  wire        CLK_A,
+    input  wire [ 8:0] A,
+    input  wire        SA,
+    input  wire [ 8:0] B,
+    output wire [17:0] Z
+);
 
+    reg [8:0] ra;
+    always @(posedge CLK_A)
+        ra <= A;
+
+    MULT9X9 # (
+        .REGINPUTA("BYPASS"),
+        .REGINPUTB("BYPASS"),
+        .REGOUTPUT("BYPASS")
+    ) mult (
+        .A       (ra),
+        .SIGNEDA (SA),
+        .B       (B),
+        .Z       (Z)
+    );
+
+endmodule

diff --git a/dsp-ff-plugin/tests/nexus_mult/nexus_mult.tcl b/dsp-ff-plugin/tests/nexus_mult/nexus_mult.tcl
index d82ffa8..1eef04a 100644
--- a/dsp-ff-plugin/tests/nexus_mult/nexus_mult.tcl
+++ b/dsp-ff-plugin/tests/nexus_mult/nexus_mult.tcl

@@ -41,3 +41,18 @@
 select -assert-count 1 t:MULT9X9
 select -assert-count 0 t:FD1P3IX
 
+# The test cannot be run because the equivalence check fails at some internal
+# wires of the DSP simulation model which ends up dangling. So that's not a
+# real issue but makes the test fail.
+
+#set TOP "mult_ctrl"
+#design -load read
+#hierarchy -top ${TOP}
+#synth_nexus -flatten
+#techmap -map +/nexus/cells_sim.v t:VLO t:VHI %u ;# Unmap VHI and VLO
+#equiv_opt -assert -async2sync -map +/nexus/cells_sim.v debug dsp_ff -rules ../../nexus-dsp_rules.txt
+#design -load postopt
+#yosys cd ${TOP}
+#stat
+#select -assert-count 1 t:MULT9X9
+#select -assert-count 0 t:FD1P3IX

diff --git a/dsp-ff-plugin/tests/nexus_mult/nexus_mult.v b/dsp-ff-plugin/tests/nexus_mult/nexus_mult.v
index 1ca806d..9836f7f 100644
--- a/dsp-ff-plugin/tests/nexus_mult/nexus_mult.v
+++ b/dsp-ff-plugin/tests/nexus_mult/nexus_mult.v

@@ -82,3 +82,33 @@
     );
 
 endmodule
+
+module mult_ctrl (
+    input  wire        CLK,
+    input  wire [ 8:0] A,
+    input  wire        SA,
+    input  wire [ 8:0] B,
+    output wire [17:0] Z
+);
+
+    reg [8:0] ra;
+    reg       rsa;
+
+    always @(posedge CLK) begin
+        ra  <= A;
+        rsa <= SA;
+    end
+
+    MULT9X9 # (
+        .REGINPUTA("BYPASS"),
+        .REGINPUTB("BYPASS"),
+        .REGOUTPUT("BYPASS")
+    ) mult (
+        .A          (ra),
+        .SIGNEDA    (rsa),
+        .B          (B),
+        .Z          (Z)
+    );
+
+endmodule
+