Introspection: Extract common code from GetNets to GetCmd Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
diff --git a/design_introspection-plugin/get_cmd.cc b/design_introspection-plugin/get_cmd.cc index b69d016..0dc6dc4 100644 --- a/design_introspection-plugin/get_cmd.cc +++ b/design_introspection-plugin/get_cmd.cc
@@ -37,9 +37,8 @@ } size_t argidx; - std::vector<std::pair<std::string, std::string>> filters; + Filters filters; bool is_quiet = false; - bool has_filter = false; // Parse command arguments for (argidx = 1; argidx < args.size(); argidx++) { @@ -79,9 +78,7 @@ filters.emplace_back(filter.substr(0, separator), filter.substr(separator + 2)); } - size_t filter_cnt = filters.size(); - has_filter = filter_cnt > 0; - if (filter_cnt > 1) { + if (filters.size() > 1) { log_warning( "Currently -filter switch supports only a single " "'equal(==)' condition expression, the rest will be " @@ -100,16 +97,16 @@ // Add name of top module to selection string std::vector<std::string> selection_args; std::transform(args.begin() + argidx, args.end(), - std::back_inserter(selection_args), [&](std::string& net) { + std::back_inserter(selection_args), [&](std::string& obj) { return RTLIL::unescape_id(top_module->name) + - "/w:" + net; + "/" + SelectionType() + ":" + obj; }); // Execute the selection extra_args(selection_args, 0, design); if (design->selected_modules().empty()) { if (!is_quiet) { - log_warning("Specified net not found in design\n"); + log_warning("Specified %s not found in design\n", TypeName().c_str()); } } @@ -117,26 +114,10 @@ Tcl_Interp* interp = yosys_get_tcl_interp(); Tcl_Obj* tcl_list = Tcl_NewListObj(0, NULL); for (auto module : design->selected_modules()) { - for (auto wire : module->selected_wires()) { - if (has_filter) { - std::pair<std::string, std::string> filter = filters.at(0); - std::string attr_value = wire->get_string_attribute( - RTLIL::IdString(RTLIL::escape_id(filter.first))); - if (attr_value.compare(filter.second)) { - continue; - } - } - if (!is_quiet) { - log("%s ", id2cstr(wire->name)); - } - Tcl_Obj* value_obj = Tcl_NewStringObj(id2cstr(wire->name), -1); - Tcl_ListObjAppendElement(interp, tcl_list, value_obj); - } + ExtractSelection(tcl_list, module, filters, is_quiet); } if (!is_quiet) { log("\n"); } Tcl_SetObjResult(interp, tcl_list); } -/* void execute(std::vector<std::string> args, RTLIL::Design* design) override; - */
diff --git a/design_introspection-plugin/get_cmd.h b/design_introspection-plugin/get_cmd.h index 6376b05..078694e 100644 --- a/design_introspection-plugin/get_cmd.h +++ b/design_introspection-plugin/get_cmd.h
@@ -6,11 +6,17 @@ USING_YOSYS_NAMESPACE struct GetCmd : public Pass { - GetCmd(const std::string& name, const std::string& description) : Pass(name, description) {} + using Filter = std::pair<std::string, std::string>; + using Filters = std::vector<Filter>; - void help() override; - void execute(std::vector<std::string> args, RTLIL::Design* design) override; - virtual std::string TypeName() = 0; + GetCmd(const std::string& name, const std::string& description) + : Pass(name, description) {} + + void help() override; + void execute(std::vector<std::string> args, RTLIL::Design* design) override; + virtual std::string TypeName() = 0; + virtual std::string SelectionType() = 0; + virtual void ExtractSelection(Tcl_Obj*, RTLIL::Module*, Filters&, bool) = 0; }; #endif // GET_CMD_H_
diff --git a/design_introspection-plugin/get_nets.cc b/design_introspection-plugin/get_nets.cc index 25ce177..d44eb63 100644 --- a/design_introspection-plugin/get_nets.cc +++ b/design_introspection-plugin/get_nets.cc
@@ -2,7 +2,25 @@ USING_YOSYS_NAMESPACE -std::string GetNets::TypeName() { - return "net"; -} +std::string GetNets::TypeName() { return "net"; } +std::string GetNets::SelectionType() { return "w"; } + +void GetNets::ExtractSelection(Tcl_Obj* tcl_list, RTLIL::Module* module, + Filters& filters, bool is_quiet) { + for (auto wire : module->selected_wires()) { + if (filters.size() > 0) { + Filter filter = filters.at(0); + std::string attr_value = wire->get_string_attribute( + RTLIL::IdString(RTLIL::escape_id(filter.first))); + if (attr_value.compare(filter.second)) { + continue; + } + } + if (!is_quiet) { + log("%s ", id2cstr(wire->name)); + } + Tcl_Obj* value_obj = Tcl_NewStringObj(id2cstr(wire->name), -1); + Tcl_ListObjAppendElement(yosys_get_tcl_interp(), tcl_list, value_obj); + } +}
diff --git a/design_introspection-plugin/get_nets.h b/design_introspection-plugin/get_nets.h index 57b9885..8af0b9f 100644 --- a/design_introspection-plugin/get_nets.h +++ b/design_introspection-plugin/get_nets.h
@@ -6,9 +6,12 @@ USING_YOSYS_NAMESPACE struct GetNets : public GetCmd { - GetNets() : GetCmd("get_nets", "Print matching nets") {} + GetNets() : GetCmd("get_nets", "Print matching nets") {} - std::string TypeName() override; + std::string TypeName() override; + std::string SelectionType() override; + void ExtractSelection(Tcl_Obj* tcl_list, RTLIL::Module* module, + Filters& filters, bool is_quiet) override; }; #endif // GET_NETS_H_