Test -U

Signed-off-by: Rafal Kapuscik <rkapuscik@antmicro.com>

systemverilog-plugin/tests/defines/defines.tcl

diff --git a/systemverilog-plugin/tests/defines/defines.tcl b/systemverilog-plugin/tests/defines/defines.tcl
index 8cd653b..030c1ad 100644
--- a/systemverilog-plugin/tests/defines/defines.tcl
+++ b/systemverilog-plugin/tests/defines/defines.tcl
@@ -8,6 +8,8 @@
 }
 
 systemverilog_defines -DPONA
+systemverilog_defines -DPAKALA
+systemverilog_defines -UPAKALA
 read_systemverilog $::env(DESIGN_TOP).v
 hierarchy
 write_verilog

systemverilog-plugin/tests/defines/defines.v

diff --git a/systemverilog-plugin/tests/defines/defines.v b/systemverilog-plugin/tests/defines/defines.v
index 407aac1..528e9f1 100644
--- a/systemverilog-plugin/tests/defines/defines.v
+++ b/systemverilog-plugin/tests/defines/defines.v
@@ -22,5 +22,8 @@
 `ifndef PONA
   initial $stop("Define failed");
 `endif
+`ifdef PAKALA
+  initial $stop("Undefine failed");
+`endif
   assign out = clk;
 endmodule