systemverilog-plugin: delete children when changing wire to id in process_assignment

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>

systemverilog-plugin/UhdmAst.cc

diff --git a/systemverilog-plugin/UhdmAst.cc b/systemverilog-plugin/UhdmAst.cc
index 23d72c0..a3484d6 100644
--- a/systemverilog-plugin/UhdmAst.cc
+++ b/systemverilog-plugin/UhdmAst.cc
@@ -2650,6 +2650,7 @@
             case AST::AST_PARAMETER:
             case AST::AST_LOCALPARAM:
                 node->type = AST::AST_IDENTIFIER;
+                delete_children(node);
                 delete_attribute(node, UhdmAst::packed_ranges());
                 delete_attribute(node, UhdmAst::unpacked_ranges());
                 break;