Added option "-nosdff" to disable synchronous set/reset flip-flop inference for k6n10f Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

diff --git a/ql-qlf-plugin/synth_quicklogic.cc b/ql-qlf-plugin/synth_quicklogic.cc
index 16dd36c..303b1de 100644
--- a/ql-qlf-plugin/synth_quicklogic.cc
+++ b/ql-qlf-plugin/synth_quicklogic.cc

@@ -84,6 +84,11 @@
         log("    -no_ff_map\n");
         log("        By default ff techmap is turned on. Specifying this switch turns it off.\n");
         log("\n");
+        log("    -nosdff\n");
+        log("        By default infer synchronous S/R flip-flops for architectures\n");
+        log("        that support them. \n");
+        log("        Specifying this switch turns it off.\n");
+        log("\n");
         log("\n");
         log("The following commands are executed by this synthesis command:\n");
         help_script();
@@ -97,6 +102,7 @@
     bool abcOpt;
     bool abc9;
     bool noffmap;
+    bool nosdff;
 
     void clear_flags() override
     {
@@ -112,6 +118,7 @@
         abc9 = true;
         noffmap = false;
         nodsp = false;
+        nosdff = false;
     }
 
     void execute(std::vector<std::string> args, RTLIL::Design *design) override
@@ -177,6 +184,10 @@
                 noffmap = true;
                 continue;
             }
+            if (args[argidx] == "-nosdff") {
+                nosdff = true;
+                continue;
+            }
 
             break;
         }
@@ -192,6 +203,10 @@
             abc9 = false;
         }
 
+        if (family == "qlf_k4n8") {
+            nosdff = true;
+        }
+
         if (abc9 && design->scratchpad_get_int("abc9.D", 0) == 0) {
             log_warning("delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.\n");
             design->scratchpad_set_int("abc9.D", 41667); // 12MHz = 83.33.. ns; divided by two to allow for interconnect delay.
@@ -230,9 +245,13 @@
         }
 
         std::string noDFFArgs;
-        if (family == "qlf_k4n8") {
-            noDFFArgs = " -nodffe -nosdff";
+        if (nosdff) {
+            noDFFArgs += " -nosdff";
         }
+        if (family == "qlf_k4n8") {
+            noDFFArgs += " -nodffe";
+        }
+
         if (check_label("coarse")) {
             run("check");
             run("opt -nodffe -nosdff");
@@ -366,7 +385,11 @@
                 // FIXME: dfflegalize seems to leave $_DLATCH_[NP]_ even if it
                 // is not allowed. So we allow them and map them later to
                 // $_DLATCHSR_[NP]NN_.
-                run("dfflegalize -cell $_DFFSRE_?NNP_ 0 -cell $_SDFFE_?N?P_ 0 -cell $_DLATCHSR_?NN_ 0 -cell $_DLATCH_?_ 0");
+                std::string legalizeArgs = " -cell $_DFFSRE_?NNP_ 0 -cell $_DLATCHSR_?NN_ 0 -cell $_DLATCH_?_ 0";
+                if (!nosdff) {
+                    legalizeArgs += " -cell $_SDFFE_?N?P_ 0";
+                }
+                run("dfflegalize" + legalizeArgs);
             } else if (family == "pp3") {
                 run("dfflegalize -cell $_DFFSRE_PPPP_ 0 -cell $_DLATCH_?_ x");
                 run("techmap -map +/quicklogic/" + family + "/cells_map.v");