SDC: Add new clock names in Buffer and Clock Divider propagation

Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>

sdc-plugin/clocks.cc

diff --git a/sdc-plugin/clocks.cc b/sdc-plugin/clocks.cc
index 3d27f70..a2c1edd 100644
--- a/sdc-plugin/clocks.cc
+++ b/sdc-plugin/clocks.cc
@@ -59,7 +59,7 @@
 	    log("create_clock -period %f -name %s -waveform {%f %f} %s\n",
 	        clock_wire.Period(), clock.first.c_str(),
 	        clock_wire.RisingEdge(), clock_wire.FallingEdge(),
-	        clock_wire.Name().c_str());
+	        clock_wire.WireName().c_str());
 	}
 #endif
     }
@@ -99,8 +99,8 @@
 	    auto pll_clock_wires = pass->FindSinkClockWiresForCellType(
 		    clock_wire, "PLLE2_ADV");
 	    for (auto pll_clock_wire : pll_clock_wires) {
-		log("PLL wire: %s\n", pll_clock_wire.Name().c_str());
-		AddClockWire(clock.first, pll_clock_wire);
+		log("PLL wire: %s\n", pll_clock_wire.WireName().c_str());
+		AddClockWire(pll_clock_wire.WireName(), pll_clock_wire);
 	    }
 	}
     }
@@ -118,7 +118,7 @@
 	for (auto wire : buf_wires) {
 	    log("%s wire: %s\n", buffer.name.c_str(), wire->name.c_str());
 	    path_delay += buffer.delay;
-	    AddClockWire(clock.first, wire, clock_wire.Period(),
+	    AddClockWire(wire->name.str(), wire, clock_wire.Period(),
 	                 clock_wire.RisingEdge() + path_delay,
 	                 clock_wire.FallingEdge() + path_delay);
 	}

sdc-plugin/clocks.h

diff --git a/sdc-plugin/clocks.h b/sdc-plugin/clocks.h
index 22c96d1..f0fe520 100644
--- a/sdc-plugin/clocks.h
+++ b/sdc-plugin/clocks.h
@@ -38,7 +38,7 @@
           rising_edge_(rising_edge),
           falling_edge_(falling_edge) {}
     RTLIL::Wire* Wire() { return wire_; }
-    std::string Name() { return RTLIL::unescape_id(wire_->name); }
+    std::string WireName() { return RTLIL::unescape_id(wire_->name); }
     float Period() { return period_; }
     float RisingEdge() { return rising_edge_; }
     float FallingEdge() { return falling_edge_; }