SDC: Add test for set_clock_groups

Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>

sdc-plugin/tests/Makefile

diff --git a/sdc-plugin/tests/Makefile b/sdc-plugin/tests/Makefile
index b2d146a..3b45b57 100644
--- a/sdc-plugin/tests/Makefile
+++ b/sdc-plugin/tests/Makefile
@@ -1,6 +1,8 @@
 # counter, counter2, pll - test buffer and clock divider propagation
 # set_false_path - test the set_false_path command
 # set_max_delay - test the set_max_delay command
+# set_clock_groups - test the set_clock_groups command
+
 TESTS = counter \
 	counter2 \
 	pll \
@@ -8,7 +10,9 @@
 	pll_fbout_phase \
 	pll_approx_equal \
 	set_false_path \
-	set_max_delay
+	set_max_delay \
+	set_clock_groups
+
 include $(shell pwd)/../../Makefile_test.common
 
 counter_verify = $(call diff_test,counter,sdc) && $(call diff_test,counter,txt)
@@ -19,3 +23,4 @@
 pll_approx_equal_verify = $(call diff_test,pll_approx_equal,sdc)
 set_false_path_verify = $(call diff_test,set_false_path,sdc)
 set_max_delay_verify = $(call diff_test,set_max_delay,sdc)
+set_clock_groups_verify = $(call diff_test,set_clock_groups,sdc)

sdc-plugin/tests/set_clock_groups/set_clock_groups.golden.sdc

diff --git a/sdc-plugin/tests/set_clock_groups/set_clock_groups.golden.sdc b/sdc-plugin/tests/set_clock_groups/set_clock_groups.golden.sdc
new file mode 100644
index 0000000..162e4d0
--- /dev/null
+++ b/sdc-plugin/tests/set_clock_groups/set_clock_groups.golden.sdc
@@ -0,0 +1,4 @@
+create_clock_groups -group clk1 clk2 
+create_clock_groups -group clk3 clk4 -group clk11 clk12 -group clk13 clk14 -asynchronous
+create_clock_groups -group clk7 clk8 -group clk9 clk10 -physically_exclusive
+create_clock_groups -group clk5 clk6 -logically_exclusive

sdc-plugin/tests/set_clock_groups/set_clock_groups.tcl

diff --git a/sdc-plugin/tests/set_clock_groups/set_clock_groups.tcl b/sdc-plugin/tests/set_clock_groups/set_clock_groups.tcl
new file mode 100644
index 0000000..5e06b2c
--- /dev/null
+++ b/sdc-plugin/tests/set_clock_groups/set_clock_groups.tcl
@@ -0,0 +1,16 @@
+yosys -import
+plugin -i sdc
+#Import the commands from the plugins to the tcl interpreter
+yosys -import
+
+read_verilog set_clock_groups.v
+# Some of symbiflow expects eblifs with only one module.
+synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp
+
+set_clock_groups -group clk1 clk2
+set_clock_groups -asynchronous -group clk3 clk4
+set_clock_groups -group clk5 clk6 -logically_exclusive
+set_clock_groups -group clk7 clk8 -physically_exclusive -group clk9 clk10
+set_clock_groups -quiet -group clk11 clk12 -asynchronous -group clk13 clk14
+
+write_sdc set_clock_groups.sdc

sdc-plugin/tests/set_clock_groups/set_clock_groups.v

diff --git a/sdc-plugin/tests/set_clock_groups/set_clock_groups.v b/sdc-plugin/tests/set_clock_groups/set_clock_groups.v
new file mode 100644
index 0000000..d40055b
--- /dev/null
+++ b/sdc-plugin/tests/set_clock_groups/set_clock_groups.v
@@ -0,0 +1,75 @@
+module top (
+	(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) input  clk,
+	output [3:0] led,
+	inout out_a,
+	output [1:0] out_b,
+	output signal_p,
+	output signal_n
+);
+
+	wire LD6, LD7, LD8, LD9;
+	wire inter_wire, inter_wire_2;
+	localparam BITS = 1;
+	localparam LOG2DELAY = 25;
+
+	reg [BITS+LOG2DELAY-1:0] counter = 0;
+
+	always @(posedge clk) begin
+		counter <= counter + 1;
+	end
+	assign led[1] = inter_wire;
+	assign inter_wire = inter_wire_2;
+	assign {LD9, LD8, LD7, LD6} = counter >> LOG2DELAY;
+	OBUFTDS OBUFTDS_2(
+		.I(LD6),
+		.O(signal_p),
+		.OB(signal_n),
+		.T(1'b1)
+	);
+	OBUF #(
+		.IOSTANDARD("LVCMOS33"),
+		.SLEW("SLOW")
+	) OBUF_6(.I(LD6), .O(led[0]));
+	OBUF #(
+		.IOSTANDARD("LVCMOS33"),
+		.SLEW("SLOW")
+	) OBUF_7(.I(LD7), .O(inter_wire_2));
+	OBUF #(
+		.IOSTANDARD("LVCMOS33"),
+		.SLEW("SLOW")
+	) OBUF_OUT(.I(LD7), .O(out_a));
+	bottom bottom_inst(.I(LD8), .O(led[2]), .OB(out_b));
+	bottom_intermediate bottom_intermediate_inst(.I(LD9), .O(led[3]));
+endmodule
+
+module bottom_intermediate (
+	input I,
+	output O
+);
+	wire bottom_intermediate_wire;
+	assign O = bottom_intermediate_wire;
+	OBUF #(
+		.IOSTANDARD("LVCMOS33"),
+		.SLEW("SLOW")
+	) OBUF_8(.I(I), .O(bottom_intermediate_wire));
+endmodule
+
+module bottom (
+	input I,
+	output [1:0] OB,
+	output O
+);
+	OBUF #(
+		.IOSTANDARD("LVCMOS33"),
+		.SLEW("SLOW")
+	) OBUF_9(.I(I), .O(O));
+	OBUF #(
+		.IOSTANDARD("LVCMOS33"),
+		.SLEW("SLOW")
+	) OBUF_10(.I(I), .O(OB[0]));
+	OBUF #(
+		.IOSTANDARD("LVCMOS33"),
+		.SLEW("SLOW")
+	) OBUF_11(.I(I), .O(OB[1]));
+endmodule
+