tests: remove -vpr flag as it was removed in yosys Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
diff --git a/design_introspection-plugin/tests/get_cells/get_cells.tcl b/design_introspection-plugin/tests/get_cells/get_cells.tcl index 861e6a9..85cc897 100644 --- a/design_introspection-plugin/tests/get_cells/get_cells.tcl +++ b/design_introspection-plugin/tests/get_cells/get_cells.tcl
@@ -5,7 +5,7 @@ read_verilog get_cells.v # Some of symbiflow expects eblifs with only one module. -synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp +synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp set fp [open "get_cells.txt" "w"]
diff --git a/design_introspection-plugin/tests/get_nets/get_nets.tcl b/design_introspection-plugin/tests/get_nets/get_nets.tcl index c4fe329..2d3083a 100644 --- a/design_introspection-plugin/tests/get_nets/get_nets.tcl +++ b/design_introspection-plugin/tests/get_nets/get_nets.tcl
@@ -5,7 +5,7 @@ read_verilog get_nets.v # Some of symbiflow expects eblifs with only one module. -synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp +synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp set fp [open "get_nets.txt" "w"]
diff --git a/design_introspection-plugin/tests/get_pins/get_pins.tcl b/design_introspection-plugin/tests/get_pins/get_pins.tcl index 144d453..e352df1 100644 --- a/design_introspection-plugin/tests/get_pins/get_pins.tcl +++ b/design_introspection-plugin/tests/get_pins/get_pins.tcl
@@ -5,7 +5,7 @@ read_verilog get_pins.v # Some of symbiflow expects eblifs with only one module. -synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp +synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp set fp [open "get_pins.txt" "w"]
diff --git a/design_introspection-plugin/tests/get_ports/get_ports.tcl b/design_introspection-plugin/tests/get_ports/get_ports.tcl index 1ac5903..eca245d 100644 --- a/design_introspection-plugin/tests/get_ports/get_ports.tcl +++ b/design_introspection-plugin/tests/get_ports/get_ports.tcl
@@ -5,7 +5,7 @@ read_verilog get_ports.v # Some of symbiflow expects eblifs with only one module. -synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp +synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp help get_ports set fp [open "get_ports.txt" "w"]
diff --git a/params-plugin/tests/pll/pll.tcl b/params-plugin/tests/pll/pll.tcl index cc6e7b3..999abad 100644 --- a/params-plugin/tests/pll/pll.tcl +++ b/params-plugin/tests/pll/pll.tcl
@@ -38,7 +38,7 @@ close $fp # Start flow after library reading -synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp -iopad -run prepare:check +synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp -iopad -run prepare:check # Map Xilinx tech library to 7-series VPR tech library. read_verilog -lib ./techmaps/cells_sim.v
diff --git a/sdc-plugin/tests/counter/counter.tcl b/sdc-plugin/tests/counter/counter.tcl index b045b3c..e68574b 100644 --- a/sdc-plugin/tests/counter/counter.tcl +++ b/sdc-plugin/tests/counter/counter.tcl
@@ -8,7 +8,7 @@ read_verilog -lib +/xilinx/cells_xtra.v hierarchy -check -auto-top # Start flow after library reading -synth_xilinx -vpr -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check +synth_xilinx -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check # Read the design's timing constraints read_sdc $::env(DESIGN_TOP).input.sdc
diff --git a/sdc-plugin/tests/counter2/counter2.tcl b/sdc-plugin/tests/counter2/counter2.tcl index 4fcf9be..809b2b8 100644 --- a/sdc-plugin/tests/counter2/counter2.tcl +++ b/sdc-plugin/tests/counter2/counter2.tcl
@@ -8,7 +8,7 @@ read_verilog -lib +/xilinx/cells_xtra.v hierarchy -check -auto-top # Start flow after library reading -synth_xilinx -vpr -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check +synth_xilinx -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check # Read the design's timing constraints read_sdc $::env(DESIGN_TOP).input.sdc
diff --git a/sdc-plugin/tests/period_check/period_check.tcl b/sdc-plugin/tests/period_check/period_check.tcl index bc613de..cdfdd25 100644 --- a/sdc-plugin/tests/period_check/period_check.tcl +++ b/sdc-plugin/tests/period_check/period_check.tcl
@@ -8,7 +8,7 @@ read_verilog -lib +/xilinx/cells_xtra.v hierarchy -check -auto-top # Start flow after library reading -synth_xilinx -vpr -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check +synth_xilinx -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check # Propagate the clocks propagate_clocks
diff --git a/sdc-plugin/tests/period_format_check/period_format_check.tcl b/sdc-plugin/tests/period_format_check/period_format_check.tcl index bc613de..cdfdd25 100644 --- a/sdc-plugin/tests/period_format_check/period_format_check.tcl +++ b/sdc-plugin/tests/period_format_check/period_format_check.tcl
@@ -8,7 +8,7 @@ read_verilog -lib +/xilinx/cells_xtra.v hierarchy -check -auto-top # Start flow after library reading -synth_xilinx -vpr -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check +synth_xilinx -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check # Propagate the clocks propagate_clocks
diff --git a/sdc-plugin/tests/pll/pll.tcl b/sdc-plugin/tests/pll/pll.tcl index 5a2e3c4..09973b8 100644 --- a/sdc-plugin/tests/pll/pll.tcl +++ b/sdc-plugin/tests/pll/pll.tcl
@@ -9,7 +9,7 @@ hierarchy -check -auto-top # Start flow after library reading -synth_xilinx -vpr -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check +synth_xilinx -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check # Read the design timing constraints read_sdc $::env(DESIGN_TOP).input.sdc
diff --git a/sdc-plugin/tests/pll_approx_equal/pll_approx_equal.tcl b/sdc-plugin/tests/pll_approx_equal/pll_approx_equal.tcl index 5a2e3c4..09973b8 100644 --- a/sdc-plugin/tests/pll_approx_equal/pll_approx_equal.tcl +++ b/sdc-plugin/tests/pll_approx_equal/pll_approx_equal.tcl
@@ -9,7 +9,7 @@ hierarchy -check -auto-top # Start flow after library reading -synth_xilinx -vpr -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check +synth_xilinx -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check # Read the design timing constraints read_sdc $::env(DESIGN_TOP).input.sdc
diff --git a/sdc-plugin/tests/pll_div/pll_div.tcl b/sdc-plugin/tests/pll_div/pll_div.tcl index 5a2e3c4..09973b8 100644 --- a/sdc-plugin/tests/pll_div/pll_div.tcl +++ b/sdc-plugin/tests/pll_div/pll_div.tcl
@@ -9,7 +9,7 @@ hierarchy -check -auto-top # Start flow after library reading -synth_xilinx -vpr -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check +synth_xilinx -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check # Read the design timing constraints read_sdc $::env(DESIGN_TOP).input.sdc
diff --git a/sdc-plugin/tests/pll_fbout_phase/pll_fbout_phase.tcl b/sdc-plugin/tests/pll_fbout_phase/pll_fbout_phase.tcl index 5a2e3c4..09973b8 100644 --- a/sdc-plugin/tests/pll_fbout_phase/pll_fbout_phase.tcl +++ b/sdc-plugin/tests/pll_fbout_phase/pll_fbout_phase.tcl
@@ -9,7 +9,7 @@ hierarchy -check -auto-top # Start flow after library reading -synth_xilinx -vpr -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check +synth_xilinx -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check # Read the design timing constraints read_sdc $::env(DESIGN_TOP).input.sdc
diff --git a/sdc-plugin/tests/set_clock_groups/set_clock_groups.tcl b/sdc-plugin/tests/set_clock_groups/set_clock_groups.tcl index 5e06b2c..223d9ec 100644 --- a/sdc-plugin/tests/set_clock_groups/set_clock_groups.tcl +++ b/sdc-plugin/tests/set_clock_groups/set_clock_groups.tcl
@@ -5,7 +5,7 @@ read_verilog set_clock_groups.v # Some of symbiflow expects eblifs with only one module. -synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp +synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp set_clock_groups -group clk1 clk2 set_clock_groups -asynchronous -group clk3 clk4
diff --git a/sdc-plugin/tests/set_false_path/set_false_path.tcl b/sdc-plugin/tests/set_false_path/set_false_path.tcl index ae14469..dd510f3 100644 --- a/sdc-plugin/tests/set_false_path/set_false_path.tcl +++ b/sdc-plugin/tests/set_false_path/set_false_path.tcl
@@ -5,7 +5,7 @@ read_verilog $::env(DESIGN_TOP).v # Some of symbiflow expects eblifs with only one module. -synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp +synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp # -to inter_wire net set_false_path -to inter_wire
diff --git a/sdc-plugin/tests/set_max_delay/set_max_delay.tcl b/sdc-plugin/tests/set_max_delay/set_max_delay.tcl index f2a5b4f..6b7f23d 100644 --- a/sdc-plugin/tests/set_max_delay/set_max_delay.tcl +++ b/sdc-plugin/tests/set_max_delay/set_max_delay.tcl
@@ -5,7 +5,7 @@ read_verilog $::env(DESIGN_TOP).v # Some of symbiflow expects eblifs with only one module. -synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp +synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp # -to inter_wire net set_max_delay 1 -to inter_wire
diff --git a/sdc-plugin/tests/waveform_check/waveform_check.tcl b/sdc-plugin/tests/waveform_check/waveform_check.tcl index bc613de..cdfdd25 100644 --- a/sdc-plugin/tests/waveform_check/waveform_check.tcl +++ b/sdc-plugin/tests/waveform_check/waveform_check.tcl
@@ -8,7 +8,7 @@ read_verilog -lib +/xilinx/cells_xtra.v hierarchy -check -auto-top # Start flow after library reading -synth_xilinx -vpr -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check +synth_xilinx -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check # Propagate the clocks propagate_clocks
diff --git a/xdc-plugin/tests/counter/counter.tcl b/xdc-plugin/tests/counter/counter.tcl index be26dde..b6ef30f 100644 --- a/xdc-plugin/tests/counter/counter.tcl +++ b/xdc-plugin/tests/counter/counter.tcl
@@ -8,7 +8,7 @@ # -flatten is used to ensure that the output eblif has only one module. # Some of symbiflow expects eblifs with only one module. -synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp +synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp #Read the design constraints read_xdc -part_json ../xc7a35tcsg324-1.json $::env(DESIGN_TOP).xdc
diff --git a/xdc-plugin/tests/io_loc_pairs/io_loc_pairs.tcl b/xdc-plugin/tests/io_loc_pairs/io_loc_pairs.tcl index be26dde..b6ef30f 100644 --- a/xdc-plugin/tests/io_loc_pairs/io_loc_pairs.tcl +++ b/xdc-plugin/tests/io_loc_pairs/io_loc_pairs.tcl
@@ -8,7 +8,7 @@ # -flatten is used to ensure that the output eblif has only one module. # Some of symbiflow expects eblifs with only one module. -synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp +synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp #Read the design constraints read_xdc -part_json ../xc7a35tcsg324-1.json $::env(DESIGN_TOP).xdc
diff --git a/xdc-plugin/tests/minilitex_ddr_arty/minilitex_ddr_arty.tcl b/xdc-plugin/tests/minilitex_ddr_arty/minilitex_ddr_arty.tcl index 34d7947..fe1c07c 100644 --- a/xdc-plugin/tests/minilitex_ddr_arty/minilitex_ddr_arty.tcl +++ b/xdc-plugin/tests/minilitex_ddr_arty/minilitex_ddr_arty.tcl
@@ -8,7 +8,7 @@ read_verilog VexRiscv_Lite.v # -flatten is used to ensure that the output eblif has only one module. # Some of symbiflow expects eblifs with only one module. -synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp +synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp #Read the design constraints read_xdc -part_json ../xc7a35tcsg324-1.json $::env(DESIGN_TOP).xdc
diff --git a/xdc-plugin/tests/package_pins/package_pins.tcl b/xdc-plugin/tests/package_pins/package_pins.tcl index 2df419a..2e0352e 100644 --- a/xdc-plugin/tests/package_pins/package_pins.tcl +++ b/xdc-plugin/tests/package_pins/package_pins.tcl
@@ -7,7 +7,7 @@ read_verilog $::env(DESIGN_TOP).v # -flatten is used to ensure that the output eblif has only one module. # Some of symbiflow expects eblifs with only one module. -synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp +synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp #Read the design constraints read_xdc -part_json ../xc7a35tcsg324-1.json $::env(DESIGN_TOP).xdc
diff --git a/xdc-plugin/tests/port_indexes/port_indexes.tcl b/xdc-plugin/tests/port_indexes/port_indexes.tcl index 283cce5..e7f8e29 100644 --- a/xdc-plugin/tests/port_indexes/port_indexes.tcl +++ b/xdc-plugin/tests/port_indexes/port_indexes.tcl
@@ -8,7 +8,7 @@ # -flatten is used to ensure that the output eblif has only one module. # Some of symbiflow expects eblifs with only one module. -synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp +synth_xilinx -flatten -abc9 -nosrl -noclkbuf -nodsp if {[info procs unknown] != ""} { rename unknown ""