Rectified cells_sim & dsp_map files

Signed-off-by: rakeshm <rakeshm@quicklogic.com>

ql-qlf-plugin/qlf_k6n10f/cells_sim.v

diff --git a/ql-qlf-plugin/qlf_k6n10f/cells_sim.v b/ql-qlf-plugin/qlf_k6n10f/cells_sim.v
index 6270f49..fc5beb4 100644
--- a/ql-qlf-plugin/qlf_k6n10f/cells_sim.v
+++ b/ql-qlf-plugin/qlf_k6n10f/cells_sim.v
@@ -685,11 +685,11 @@
 
 (* blackbox *)
 module QL_DSP2 ( // TODO: Name subject to change
-    input  [NBITS_A-1:0] a,
-    input  [NBITS_B-1:0] b,
-    input  [NBITS_AF-1:0] acc_fir,
-    output [NBITS_Z-1:0] z,
-    output [NBITS_B-1:0] dly_b,
+      input  [19:0] a,
+      input  [17:0] b,
+      input  [3:0] acc_fir,
+      output [37:0] z,
+      output [17:0] dly_b,
 
     (* clkbuf_sink *)
     input         clk,
@@ -709,10 +709,10 @@
     input         register_inputs
 );
 
-    parameter [NBITS_COEF-1:0] COEFF_0 = 20'd0;
-    parameter [NBITS_COEF-1:0] COEFF_1 = 20'd0;
-    parameter [NBITS_COEF-1:0] COEFF_2 = 20'd0;
-    parameter [NBITS_COEF-1:0] COEFF_3 = 20'd0;
+    parameter [19:0] COEFF_0 = 20'd0;
+    parameter [19:0] COEFF_1 = 20'd0;
+    parameter [19:0] COEFF_2 = 20'd0;
+    parameter [19:0] COEFF_3 = 20'd0;
 
       localparam NBITS_ACC = 64;
       localparam NBITS_A = 20;
@@ -852,7 +852,7 @@
     input [NBITS_A-1:0] a_i,
     input [NBITS_B-1:0] b_i,
     output [NBITS_Z-1:0] z_o,
-    output [NBITS_B-1:0] dly_b_o,
+    output reg [NBITS_B-1:0] dly_b_o,
 
     input [NBITS_AF-1:0] acc_fir_i,
     input [2:0] feedback_i,
@@ -896,6 +896,7 @@
     reg			r_subtract;
     reg			r_sat;
     reg			r_rnd;
+    reg [NBITS_ACC-1:0] acc;
 
     always @(posedge clock_i or negedge reset_n_i) begin
         if (~reset_n_i) begin
@@ -949,11 +950,6 @@
     // Shift right control
     wire [5:0] shift_d1 = register_inputs_i ? r_shift_d1 : shift_right_i;
     wire [5:0] shift_d2 = output_select_i[1] ? shift_d1 : r_shift_d2;
-    //localparam SHIFT_SEL = {register_inputs_i, output_select_i[1]};
-    //wire [5:0] shift_right = (SHIFT_SEL == 2'b00) ?   shift_right_i :
-                             //(SHIFT_SEL == 2'b01) ?   r_shift_d1 :
-                             //(SHIFT_SEL == 2'b10) ?   r_shift_d1 :
-                           //[>(SHIFT_SEL == 2'b11) ?<] r_shift_d2;
 
     // Multiplier
     wire unsigned_mode = unsigned_a & unsigned_b;
@@ -996,8 +992,7 @@
 
     wire [NBITS_ACC-1:0] add_o = add_a + add_b;
 
-    // Accumulator
-    reg [NBITS_ACC-1:0] acc;
+    // Accumulator    
     always @(posedge clock_i or negedge reset_n_i)
         if (~reset_n_i) acc <= 'h0;
         else begin
@@ -1052,8 +1047,6 @@
 					       z1;	// if output_select_i == 3'h7
 
     // B input delayed passthrough
-    reg [NBITS_B-1:0] dly_b_o;
-
     always @(posedge clock_i or negedge reset_n_i)
         if (!reset_n_i)
             dly_b_o <= 0;

ql-qlf-plugin/qlf_k6n10f/dsp_final_map.v

diff --git a/ql-qlf-plugin/qlf_k6n10f/dsp_final_map.v b/ql-qlf-plugin/qlf_k6n10f/dsp_final_map.v
index b8423e5..0ae6f3b 100644
--- a/ql-qlf-plugin/qlf_k6n10f/dsp_final_map.v
+++ b/ql-qlf-plugin/qlf_k6n10f/dsp_final_map.v
@@ -109,7 +109,7 @@
     ) _TECHMAP_REPLACE_ (
         .a                  ({10'd0, a_i}),
         .b                  ({ 9'd0, b_i}),
-        .acc_fir            (acc_fir_i),
+        .acc_fir            ({ 2'd0, acc_fir_i}),
         .z                  (z),
         .dly_b              (dly_b),
 

ql-qlf-plugin/qlf_k6n10f/dsp_map.v

diff --git a/ql-qlf-plugin/qlf_k6n10f/dsp_map.v b/ql-qlf-plugin/qlf_k6n10f/dsp_map.v
index e10df2a..9606c4f 100644
--- a/ql-qlf-plugin/qlf_k6n10f/dsp_map.v
+++ b/ql-qlf-plugin/qlf_k6n10f/dsp_map.v
@@ -70,10 +70,10 @@
     dsp_t1_10x9x32 _TECHMAP_REPLACE_ (
         .a_i                (a),
         .b_i                (b),
-        .acc_fir_i          (3'd0),
+        .acc_fir_i          (2'd0),
         .z_o                (z),
 
-        .feedback_i         (2'd0),
+        .feedback_i         (3'd0),
         .load_acc_i         (1'b0),
         .unsigned_a_i       (!A_SIGNED),
         .unsigned_b_i       (!B_SIGNED),