SDC: Add test for approximate equality on input clock Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
diff --git a/sdc-plugin/tests/Makefile b/sdc-plugin/tests/Makefile index ea5e5a1..d19f19d 100644 --- a/sdc-plugin/tests/Makefile +++ b/sdc-plugin/tests/Makefile
@@ -1,4 +1,4 @@ -TESTS = counter counter2 pll pll_div pll_fbout_phase +TESTS = counter counter2 pll pll_div pll_fbout_phase pll_approx_equal .PHONY: $(TESTS) counter_verify = $(call compare,counter,sdc) && $(call compare,counter,txt) @@ -6,6 +6,7 @@ pll_verify = $(call compare,pll,sdc) pll_div_verify = $(call compare,pll_div,sdc) pll_fbout_phase_verify = $(call compare,pll_fbout_phase,sdc) +pll_approx_equal_verify = $(call compare,pll_approx_equal,sdc) all: $(TESTS) compare = diff $(1)/$(1).golden.$(2) $(1)/$(1).$(2)
diff --git a/sdc-plugin/tests/pll_approx_equal/pll_approx_equal.golden.sdc b/sdc-plugin/tests/pll_approx_equal/pll_approx_equal.golden.sdc new file mode 100644 index 0000000..c27b90a --- /dev/null +++ b/sdc-plugin/tests/pll_approx_equal/pll_approx_equal.golden.sdc
@@ -0,0 +1,8 @@ +create_clock -period 10 -waveform {0 5} \$auto\$clkbufmap.cc:247:execute\$1829 +create_clock -period 10 -waveform {0 5} \$techmap1716\FDCE_0.C +create_clock -period 9.91 -waveform {0 4.955} \$auto\$clkbufmap.cc:247:execute\$1831 +create_clock -period 9.91 -waveform {0 4.955} main_clkout_x1 +create_clock -period 4.955 -waveform {-2.4775 0} \$auto\$clkbufmap.cc:247:execute\$1833 +create_clock -period 4.955 -waveform {-2.4775 0} main_clkout_x2 +create_clock -period 2.4775 -waveform {-1.85812 -0.619375} \$auto\$clkbufmap.cc:247:execute\$1835 +create_clock -period 2.4775 -waveform {-1.85812 -0.619375} main_clkout_x4
diff --git a/sdc-plugin/tests/pll_approx_equal/pll_approx_equal.input.sdc b/sdc-plugin/tests/pll_approx_equal/pll_approx_equal.input.sdc new file mode 100644 index 0000000..00354d7 --- /dev/null +++ b/sdc-plugin/tests/pll_approx_equal/pll_approx_equal.input.sdc
@@ -0,0 +1 @@ +create_clock -period 10 -waveform {0 5} clk
diff --git a/sdc-plugin/tests/pll_approx_equal/pll_approx_equal.tcl b/sdc-plugin/tests/pll_approx_equal/pll_approx_equal.tcl new file mode 100644 index 0000000..13c8890 --- /dev/null +++ b/sdc-plugin/tests/pll_approx_equal/pll_approx_equal.tcl
@@ -0,0 +1,21 @@ +yosys -import +plugin -i sdc +# Import the commands from the plugins to the tcl interpreter +yosys -import + +read_verilog pll_approx_equal.v +read_verilog -specify -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v +read_verilog -lib +/xilinx/cells_xtra.v +hierarchy -check -auto-top + +# Start flow after library reading +synth_xilinx -vpr -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check + +# Read the design timing constraints +read_sdc $::env(INPUT_SDC_FILE) + +# Propagate the clocks +propagate_clocks + +# Write out the SDC file after the clock propagation step +write_sdc $::env(OUTPUT_SDC_FILE)
diff --git a/sdc-plugin/tests/pll_approx_equal/pll_approx_equal.v b/sdc-plugin/tests/pll_approx_equal/pll_approx_equal.v new file mode 100644 index 0000000..9b2e13a --- /dev/null +++ b/sdc-plugin/tests/pll_approx_equal/pll_approx_equal.v
@@ -0,0 +1,91 @@ +module top( + input clk, + input cpu_reset, + input data_in, + output[5:0] data_out +); + +wire [5:0] data_out; +wire builder_pll_fb; +wire fdce_0_out, fdce_1_out; +wire main_locked; + +FDCE FDCE_0 ( + .D(data_in), + .C(clk), + .CE(1'b1), + .CLR(1'b0), + .Q(fdce_0_out) +); + +FDCE FDCE_1 ( + .D(fdce_0_out), + .C(clk), + .CE(1'b1), + .CLR(1'b0), + .Q(data_out[0]) +); + +PLLE2_ADV #( + .CLKFBOUT_MULT(4'd12), + .CLKFBOUT_PHASE(90.0), + .CLKIN1_PERIOD(9.91), + .CLKOUT0_DIVIDE(4'd12), + .CLKOUT0_PHASE(90.0), + .CLKOUT1_DIVIDE(3'd6), + .CLKOUT1_PHASE(0.0), + .CLKOUT2_DIVIDE(2'd3), + .CLKOUT2_PHASE(90.0), + .REF_JITTER1(0.01), + .STARTUP_WAIT("FALSE") +) PLLE2_ADV ( + .CLKFBIN(builder_pll_fb), + .CLKIN1(clk), + .RST(cpu_reset), + .CLKFBOUT(builder_pll_fb), + .CLKOUT0(main_clkout_x1), + .CLKOUT1(main_clkout_x2), + .CLKOUT2(main_clkout_x4), + .LOCKED(main_locked) +); + +FDCE FDCE_PLLx1_PH90 ( + .D(data_in), + .C(main_clkout_x1), + .CE(1'b1), + .CLR(1'b0), + .Q(data_out[1]) +); + +FDCE FDCE_PLLx4_PH0_0 ( + .D(data_in), + .C(main_clkout_x2), + .CE(1'b1), + .CLR(1'b0), + .Q(data_out[2]) +); + +FDCE FDCE_PLLx4_PH0_1 ( + .D(data_in), + .C(main_clkout_x2), + .CE(1'b1), + .CLR(1'b0), + .Q(data_out[3]) +); + +FDCE FDCE_PLLx4_PH0_2 ( + .D(data_in), + .C(main_clkout_x2), + .CE(1'b1), + .CLR(1'b0), + .Q(data_out[4]) +); + +FDCE FDCE_PLLx2_PH90_0 ( + .D(data_in), + .C(main_clkout_x4), + .CE(1'b1), + .CLR(1'b0), + .Q(data_out[5]) +); +endmodule