SDC: Add more test cases for create_clock Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>

diff --git a/sdc-plugin/tests/Makefile b/sdc-plugin/tests/Makefile
index 400d516..68c3e45 100644
--- a/sdc-plugin/tests/Makefile
+++ b/sdc-plugin/tests/Makefile

@@ -1,7 +1,8 @@
-TESTS = counter pll
+TESTS = counter counter2 pll
 .PHONY: $(TESTS)
 
 counter_verify = $(call compare,counter,sdc) && $(call compare,counter,txt)
+counter2_verify = $(call compare,counter2,sdc) && $(call compare,counter2,txt)
 pll_verify = $(call compare,pll,sdc)
 
 all: $(TESTS)

diff --git a/sdc-plugin/tests/counter2/counter.txt b/sdc-plugin/tests/counter2/counter.txt
new file mode 100644
index 0000000..065b110
--- /dev/null
+++ b/sdc-plugin/tests/counter2/counter.txt

@@ -0,0 +1 @@
+clk_int_1 clk ibuf_proxy_out {$auto$clkbufmap.cc:247:execute$1918} {$auto$clkbufmap.cc:247:execute$1920} middle_inst_1.clk_int middle_inst_4.clk

diff --git a/sdc-plugin/tests/counter2/counter2.golden.sdc b/sdc-plugin/tests/counter2/counter2.golden.sdc
new file mode 100644
index 0000000..b3e8cca
--- /dev/null
+++ b/sdc-plugin/tests/counter2/counter2.golden.sdc

@@ -0,0 +1,6 @@
+create_clock -period 10 -waveform {0 5} clk_int_1
+create_clock -period 10 -waveform {0 5} ibuf_proxy_out
+create_clock -period 10 -waveform {0 5} \$auto\$clkbufmap.cc:247:execute\$1918
+create_clock -period 10 -waveform {1 6} \$auto\$clkbufmap.cc:247:execute\$1920
+create_clock -period 10 -waveform {1 6} middle_inst_1.clk_int
+create_clock -period 10 -waveform {2 7} middle_inst_4.clk

diff --git a/sdc-plugin/tests/counter2/counter2.golden.txt b/sdc-plugin/tests/counter2/counter2.golden.txt
new file mode 100644
index 0000000..ca1b187
--- /dev/null
+++ b/sdc-plugin/tests/counter2/counter2.golden.txt

@@ -0,0 +1 @@
+clk_int_1 clk clk2 ibuf_proxy_out {$auto$clkbufmap.cc:247:execute$1918} {$auto$clkbufmap.cc:247:execute$1920} middle_inst_1.clk_int middle_inst_4.clk

diff --git a/sdc-plugin/tests/counter2/counter2.input.sdc b/sdc-plugin/tests/counter2/counter2.input.sdc
new file mode 100644
index 0000000..3b1ac05
--- /dev/null
+++ b/sdc-plugin/tests/counter2/counter2.input.sdc

@@ -0,0 +1,3 @@
+create_clock -period 10.0 -waveform {0.000 5.000} clk_int_1
+create_clock -period 10.0 clk
+create_clock -period 10.0 -waveform {1.000 6.000} clk2

diff --git a/sdc-plugin/tests/counter2/counter2.tcl b/sdc-plugin/tests/counter2/counter2.tcl
new file mode 100644
index 0000000..80bce1b
--- /dev/null
+++ b/sdc-plugin/tests/counter2/counter2.tcl

@@ -0,0 +1,26 @@
+yosys -import
+plugin -i sdc
+# Import the commands from the plugins to the tcl interpreter
+yosys -import
+
+read_verilog counter2.v
+read_verilog -specify -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v
+read_verilog -lib +/xilinx/cells_xtra.v
+hierarchy -check -auto-top
+# Start flow after library reading
+synth_xilinx -vpr -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check
+
+# Read the design's timing constraints
+read_sdc $::env(INPUT_SDC_FILE)
+
+# Propagate the clocks
+propagate_clocks
+
+# Write the clocks to file
+set fh [open counter2.txt w]
+set clocks [get_clocks]
+puts $fh $clocks
+close $fh
+
+# Write out the SDC file after the clock propagation step
+write_sdc $::env(OUTPUT_SDC_FILE)

diff --git a/sdc-plugin/tests/counter2/counter2.v b/sdc-plugin/tests/counter2/counter2.v
new file mode 100644
index 0000000..564fae5
--- /dev/null
+++ b/sdc-plugin/tests/counter2/counter2.v

@@ -0,0 +1,36 @@
+module top(input clk,
+        input clk2,
+	input [1:0] in,
+	output [5:0] out );
+
+reg [1:0] cnt = 0;
+wire clk_int_1, clk_int_2;
+IBUF ibuf_proxy(.I(clk), .O(ibuf_proxy_out));
+IBUF ibuf_inst(.I(ibuf_proxy_out), .O(ibuf_out));
+assign clk_int_1 = ibuf_out;
+assign clk_int_2 = clk_int_1;
+
+always @(posedge clk_int_2) begin
+	cnt <= cnt + 1;
+end
+
+middle middle_inst_1(.clk(ibuf_out), .out(out[2]));
+middle middle_inst_2(.clk(clk_int_1), .out(out[3]));
+middle middle_inst_3(.clk(clk_int_2), .out(out[4]));
+middle middle_inst_4(.clk(clk2), .out(out[5]));
+
+assign out[1:0] = {cnt[0], in[0]};
+endmodule
+
+module middle(input clk,
+	output out);
+
+reg [1:0] cnt = 0;
+wire clk_int;
+assign clk_int = clk;
+always @(posedge clk_int) begin
+	cnt <= cnt + 1;
+end
+
+assign out = cnt[0];
+endmodule