Fixed simulation model for sh_dff, added missing techmap for _SHREG_DFF_P_
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
diff --git a/ql-qlf-plugin/qlf_k6n10f/cells_sim.v b/ql-qlf-plugin/qlf_k6n10f/cells_sim.v
index ded97d4..5da2aae 100644
--- a/ql-qlf-plugin/qlf_k6n10f/cells_sim.v
+++ b/ql-qlf-plugin/qlf_k6n10f/cells_sim.v
@@ -23,11 +23,11 @@
(* clkbuf_sink *)
input wire C
);
- parameter [0:0] INIT = 1'b0;
- initial Q = INIT;
+ initial Q <= 1'b0;
always @(posedge C)
- Q <= D;
+ Q <= D;
+
endmodule
(* abc9_box, lib_blackbox *)
