integrateinv-plugin/tests/single_bit/single_bit.tcl

yosys -import
plugin -i integrateinv

read_verilog -icells $::env(DESIGN_TOP).v
hierarchy -check -auto-top

debug integrateinv

select t:\$_NOT_ -assert-count 2
select t:box r:INV_A=1'b0 %i -assert-count 1
select t:box r:INV_C=1'b1 %i -assert-count 1