| // Copyright 2020-2022 F4PGA Authors | 
 | // | 
 | // Licensed under the Apache License, Version 2.0 (the "License"); | 
 | // you may not use this file except in compliance with the License. | 
 | // You may obtain a copy of the License at | 
 | // | 
 | //     http://www.apache.org/licenses/LICENSE-2.0 | 
 | // | 
 | // Unless required by applicable law or agreed to in writing, software | 
 | // distributed under the License is distributed on an "AS IS" BASIS, | 
 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | 
 | // See the License for the specific language governing permissions and | 
 | // limitations under the License. | 
 | // | 
 | // SPDX-License-Identifier: Apache-2.0 | 
 |  | 
 | module full_adder ( | 
 |     input  wire [`WIDTH-1:0] A, | 
 |     input  wire [`WIDTH-1:0] B, | 
 |     output wire [`WIDTH  :0] S, | 
 | ); | 
 |  | 
 |     // Implicit adder | 
 |     assign S = A + B; | 
 |  | 
 | endmodule | 
 |  | 
 | module subtractor ( | 
 |     input  wire [`WIDTH-1:0] A, | 
 |     input  wire [`WIDTH-1:0] B, | 
 |     output wire [`WIDTH  :0] S, | 
 | ); | 
 |  | 
 |     // Implicit subtractor | 
 |     assign S = A - B; | 
 |  | 
 | endmodule | 
 |  | 
 | module comparator ( | 
 |     input  wire [`WIDTH-1:0] A, | 
 |     input  wire [`WIDTH-1:0] B, | 
 |     output wire CO, | 
 | ); | 
 |     assign CO = (A <= B) ? 1'b1 : 1'b0; | 
 |  | 
 | endmodule |