Added clkbuf_sink attributes to qlf_k6n10f DSP cells

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

ql-qlf-plugin/qlf_k6n10f/cells_sim.v

diff --git a/ql-qlf-plugin/qlf_k6n10f/cells_sim.v b/ql-qlf-plugin/qlf_k6n10f/cells_sim.v
index 93fa6e9..c583dda 100644
--- a/ql-qlf-plugin/qlf_k6n10f/cells_sim.v
+++ b/ql-qlf-plugin/qlf_k6n10f/cells_sim.v
@@ -689,6 +689,7 @@
     input  [17:0] b_i,
     output [63:0] z_o,
 
+    (* clkbuf_sink *)
     input         clock_i,
     input         reset_i,
     input         load_acc_i,
@@ -709,6 +710,7 @@
     input  [ 8:0] b_i,
     output [31:0] z_o,
 
+    (* clkbuf_sink *)
     input         clock_i,
     input         reset_i,
     input         load_acc_i,