Add test for translate_off...translate_on sections.
diff --git a/systemverilog-plugin/tests/Makefile b/systemverilog-plugin/tests/Makefile index 4312522..94f6563 100644 --- a/systemverilog-plugin/tests/Makefile +++ b/systemverilog-plugin/tests/Makefile
@@ -21,7 +21,8 @@ report-flag \ defines \ defaults \ - formal + formal \ + translate_off include $(shell pwd)/../../Makefile_test.common @@ -33,3 +34,4 @@ defaults_verify = true defines_verify = true formal_verify = true +translate_off_verify = true
diff --git a/systemverilog-plugin/tests/translate_off/translate_off.tcl b/systemverilog-plugin/tests/translate_off/translate_off.tcl new file mode 100644 index 0000000..d7e0478 --- /dev/null +++ b/systemverilog-plugin/tests/translate_off/translate_off.tcl
@@ -0,0 +1,10 @@ +yosys -import +if { [info procs read_uhdm] == {} } { plugin -i systemverilog } +yosys -import ;# ingest plugin commands + +set TMP_DIR /tmp +if { [info exists ::env(TMPDIR) ] } { + set TMP_DIR $::env(TMPDIR) +} + +read_systemverilog -o $TMP_DIR/translate_off-test $::env(DESIGN_TOP).v
diff --git a/systemverilog-plugin/tests/translate_off/translate_off.v b/systemverilog-plugin/tests/translate_off/translate_off.v new file mode 100644 index 0000000..3ca8840 --- /dev/null +++ b/systemverilog-plugin/tests/translate_off/translate_off.v
@@ -0,0 +1,22 @@ +// Copyright 2020-2023 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 + +module top(input i, output o); + // synopsys translate_off + initial $stop("Code between translate_off...translate_on should be ignored."); + // synopsys translate_on + assign o = i; +endmodule