blob: 4c542cff1caaf07b5e903902db5a2516d7beddf9 [file] [log] [blame]
module full_adder (
input wire [`WIDTH-1:0] A,
input wire [`WIDTH-1:0] B,
output wire [`WIDTH :0] S,
);
// Implicit adder
assign S = A + B;
endmodule
module subtractor (
input wire [`WIDTH-1:0] A,
input wire [`WIDTH-1:0] B,
output wire [`WIDTH :0] S,
);
// Implicit subtractor
assign S = A - B;
endmodule