Introspection: Add test for get_cells Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
diff --git a/design_introspection-plugin/tests/Makefile b/design_introspection-plugin/tests/Makefile index 6eed865..f89ce42 100644 --- a/design_introspection-plugin/tests/Makefile +++ b/design_introspection-plugin/tests/Makefile
@@ -1,8 +1,9 @@ -TESTS = get_nets get_ports +TESTS = get_nets get_ports get_cells .PHONY: $(TESTS) get_nets_verify = $(call compare,get_nets,txt) get_ports_verify = $(call compare,get_ports,txt) +get_cells_verify = $(call compare,get_cells,txt) all: $(TESTS) compare = diff $(1)/$(1).golden.$(2) $(1)/$(1).$(2)
diff --git a/design_introspection-plugin/tests/get_cells/get_cells.golden.txt b/design_introspection-plugin/tests/get_cells/get_cells.golden.txt new file mode 100644 index 0000000..d33818d --- /dev/null +++ b/design_introspection-plugin/tests/get_cells/get_cells.golden.txt
@@ -0,0 +1,15 @@ + +*inter* cells quiet +bottom_intermediate_inst.OBUF_8 + +*inter* cells +bottom_intermediate_inst.OBUF_8 + +*inter* cells with invalid filter expression +bottom_intermediate_inst.OBUF_8 + +Filtered cells +OBUFTDS_2 + +All cells +{$abc$2135$lut$not$aiger2134$1} {$auto$alumacc.cc:485:replace_alu$1469.slice[0].carry4_1st_full} {$auto$alumacc.cc:485:replace_alu$1469.slice[0].plug} {$auto$alumacc.cc:485:replace_alu$1469.slice[1].carry4_full} {$auto$alumacc.cc:485:replace_alu$1469.slice[1].plug} {$auto$alumacc.cc:485:replace_alu$1469.slice[2].carry4_full} {$auto$alumacc.cc:485:replace_alu$1469.slice[2].plug} {$auto$alumacc.cc:485:replace_alu$1469.slice[3].carry4_full} {$auto$alumacc.cc:485:replace_alu$1469.slice[3].plug} {$auto$alumacc.cc:485:replace_alu$1469.slice[4].carry4_full} {$auto$alumacc.cc:485:replace_alu$1469.slice[4].plug} {$auto$alumacc.cc:485:replace_alu$1469.slice[5].carry4_full} {$auto$alumacc.cc:485:replace_alu$1469.slice[5].plug} {$auto$alumacc.cc:485:replace_alu$1469.slice[6].carry4_part} {$auto$simplemap.cc:420:simplemap_dff$1476} {$auto$simplemap.cc:420:simplemap_dff$1477} {$auto$simplemap.cc:420:simplemap_dff$1478} {$auto$simplemap.cc:420:simplemap_dff$1479} {$auto$simplemap.cc:420:simplemap_dff$1480} {$auto$simplemap.cc:420:simplemap_dff$1481} {$auto$simplemap.cc:420:simplemap_dff$1482} {$auto$simplemap.cc:420:simplemap_dff$1483} {$auto$simplemap.cc:420:simplemap_dff$1484} {$auto$simplemap.cc:420:simplemap_dff$1485} {$auto$simplemap.cc:420:simplemap_dff$1486} {$auto$simplemap.cc:420:simplemap_dff$1487} {$auto$simplemap.cc:420:simplemap_dff$1488} {$auto$simplemap.cc:420:simplemap_dff$1489} {$auto$simplemap.cc:420:simplemap_dff$1490} {$auto$simplemap.cc:420:simplemap_dff$1491} {$auto$simplemap.cc:420:simplemap_dff$1492} {$auto$simplemap.cc:420:simplemap_dff$1493} {$auto$simplemap.cc:420:simplemap_dff$1494} {$auto$simplemap.cc:420:simplemap_dff$1495} {$auto$simplemap.cc:420:simplemap_dff$1496} {$auto$simplemap.cc:420:simplemap_dff$1497} {$auto$simplemap.cc:420:simplemap_dff$1498} {$auto$simplemap.cc:420:simplemap_dff$1499} {$auto$simplemap.cc:420:simplemap_dff$1500} {$auto$simplemap.cc:420:simplemap_dff$1501} {$iopadmap$top.clk} OBUFTDS_2 OBUF_6 OBUF_7 OBUF_OUT bottom_inst.OBUF_10 bottom_inst.OBUF_11 bottom_inst.OBUF_9 bottom_intermediate_inst.OBUF_8
diff --git a/design_introspection-plugin/tests/get_cells/get_cells.tcl b/design_introspection-plugin/tests/get_cells/get_cells.tcl new file mode 100644 index 0000000..861e6a9 --- /dev/null +++ b/design_introspection-plugin/tests/get_cells/get_cells.tcl
@@ -0,0 +1,33 @@ +yosys -import +plugin -i design_introspection +#Import the commands from the plugins to the tcl interpreter +yosys -import + +read_verilog get_cells.v +# Some of symbiflow expects eblifs with only one module. +synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp + + +set fp [open "get_cells.txt" "w"] + +puts "\n*inter* cells quiet" +puts $fp "\n*inter* cells quiet" +puts $fp [get_cells -quiet *inter*] + +puts "\n*inter* cells" +puts $fp "\n*inter* cells" +puts $fp [get_cells *inter*] + +puts "\n*inter* cells with invalid filter expression" +puts $fp "\n*inter* cells with invalid filter expression" +puts $fp [get_cells -filter {mr_ff != true} *inter* ] + +puts "\nFiltered cells" +puts $fp "\nFiltered cells" +puts $fp [get_cells -filter {mr_ff == true || async_reg == true && dont_touch == true} ] + +puts "\nAll cells" +puts $fp "\nAll cells" +puts $fp [get_cells] + +close $fp
diff --git a/design_introspection-plugin/tests/get_cells/get_cells.v b/design_introspection-plugin/tests/get_cells/get_cells.v new file mode 100644 index 0000000..e2af7fc --- /dev/null +++ b/design_introspection-plugin/tests/get_cells/get_cells.v
@@ -0,0 +1,77 @@ +module top ( + (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) input clk, + output [3:0] led, + inout out_a, + output [1:0] out_b, + output signal_p, + output signal_n +); + + wire LD6, LD7, LD8, LD9; + wire inter_wire, inter_wire_2; + localparam BITS = 1; + localparam LOG2DELAY = 25; + + reg [BITS+LOG2DELAY-1:0] counter = 0; + + always @(posedge clk) begin + counter <= counter + 1; + end + assign led[1] = inter_wire; + assign inter_wire = inter_wire_2; + assign {LD9, LD8, LD7, LD6} = counter >> LOG2DELAY; + (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) + OBUFTDS OBUFTDS_2( + .I(LD6), + .O(signal_p), + .OB(signal_n), + .T(1'b1) + ); + (* async_reg = "false", mr_ff = "false", dont_touch = "true" *) + OBUF #( + .IOSTANDARD("LVCMOS33"), + .SLEW("SLOW") + ) OBUF_6(.I(LD6), .O(led[0])); + OBUF #( + .IOSTANDARD("LVCMOS33"), + .SLEW("SLOW") + ) OBUF_7(.I(LD7), .O(inter_wire_2)); + OBUF #( + .IOSTANDARD("LVCMOS33"), + .SLEW("SLOW") + ) OBUF_OUT(.I(LD7), .O(out_a)); + bottom bottom_inst(.I(LD8), .O(led[2]), .OB(out_b)); + bottom_intermediate bottom_intermediate_inst(.I(LD9), .O(led[3])); +endmodule + +module bottom_intermediate ( + input I, + output O +); + wire bottom_intermediate_wire; + assign O = bottom_intermediate_wire; + OBUF #( + .IOSTANDARD("LVCMOS33"), + .SLEW("SLOW") + ) OBUF_8(.I(I), .O(bottom_intermediate_wire)); +endmodule + +module bottom ( + input I, + output [1:0] OB, + output O +); + OBUF #( + .IOSTANDARD("LVCMOS33"), + .SLEW("SLOW") + ) OBUF_9(.I(I), .O(O)); + OBUF #( + .IOSTANDARD("LVCMOS33"), + .SLEW("SLOW") + ) OBUF_10(.I(I), .O(OB[0])); + OBUF #( + .IOSTANDARD("LVCMOS33"), + .SLEW("SLOW") + ) OBUF_11(.I(I), .O(OB[1])); +endmodule +