ql-qlf: qlf_k6n10f: bram: rewrite BRAM36_TDP techmap Signed-off-by: Paweł Czarnecki <pczarnecki@antmicro.com>
diff --git a/ql-qlf-plugin/qlf_k6n10f/brams_map.v b/ql-qlf-plugin/qlf_k6n10f/brams_map.v index be0b230..46f56fa 100644 --- a/ql-qlf-plugin/qlf_k6n10f/brams_map.v +++ b/ql-qlf-plugin/qlf_k6n10f/brams_map.v
@@ -6,17 +6,25 @@ // // SPDX-License-Identifier:ISC -module \$__QLF_FACTOR_BRAM36_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); +module \$__QLF_FACTOR_BRAM36_TDP (A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN, C1ADDR, C1DATA, C1EN, CLK1, CLK2, D1ADDR, D1DATA, D1EN); parameter CFG_ABITS = 10; parameter CFG_DBITS = 36; parameter CFG_ENABLE_B = 4; + parameter CFG_ENABLE_D = 4; parameter CLKPOL2 = 1; parameter CLKPOL3 = 1; parameter [36863:0] INIT = 36864'bx; + localparam MODE_36 = 3'b111; // 36 or 32-bit + localparam MODE_18 = 3'b110; // 18 or 16-bit + localparam MODE_9 = 3'b101; // 9 or 8-bit + localparam MODE_4 = 3'b100; // 4-bit + localparam MODE_2 = 3'b010; // 32-bit + localparam MODE_1 = 3'b001; // 32-bit + + input CLK1; input CLK2; - input CLK3; input [CFG_ABITS-1:0] A1ADDR; output [CFG_DBITS-1:0] A1DATA; @@ -26,106 +34,246 @@ input [CFG_DBITS-1:0] B1DATA; input [CFG_ENABLE_B-1:0] B1EN; - wire [14:0] A1ADDR_15; - wire [14:0] B1ADDR_15; - //wire [7:0] B1EN_8 = //B1EN; + input [CFG_ABITS-1:0] C1ADDR; + output [CFG_DBITS-1:0] C1DATA; + input C1EN; - wire [3:0] DIP, DOP; - wire [31:0] DI, DO; + input [CFG_ABITS-1:0] D1ADDR; + input [CFG_DBITS-1:0] D1DATA; + input [CFG_ENABLE_B-1:0] D1EN; - wire [31:0] DOBDO; - wire [3:0] DOPBDOP; + wire FLUSH1; + wire FLUSH2; + wire SPLIT; + wire [10:0] UPAE1; + wire [10:0] UPAF1; + wire [10:0] UPAE2; + wire [10:0] UPAF2; + wire SYNC_FIFO1; + wire SYNC_FIFO2; + wire FMODE1; + wire FMODE2; + wire POWERDN1; + wire POWERDN2; + wire SLEEP1; + wire SLEEP2; + wire PROTECT1; + wire PROTECT2; + wire [8:0] RAM_ID_i; - //wire [2:0] WRITEDATAWIDTHB; - //wire [2:0] READDATAWIDTHA; - assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] }; - assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA; + wire PL_INIT_i; + wire PL_ENA_i; + wire PL_REN_i; + wire PL_CLK_i; + wire [1:0] PL_WEN_i; + wire [23:0] PL_ADDR_i; + wire [35:0] PL_DATA_i; + reg PL_INIT_o; + reg PL_ENA_o; + reg PL_REN_o; + reg PL_CLK_o; + reg [1:0] PL_WEN_o; + reg [23:0] PL_ADDR_o; + wire [35:0] PL_DATA_o; - assign A1ADDR_15[14:CFG_ABITS] = 0; - assign A1ADDR_15[CFG_ABITS-1:0] = A1ADDR; - assign B1ADDR_15[14:CFG_ABITS] = 0; - assign B1ADDR_15[CFG_ABITS-1:0] = B1ADDR; + wire [2:0] WMODE; + wire [2:0] RMODE; - /*if (CFG_DBITS == 1) begin - assign WRITEDATAWIDTHB = 3'b000; - assign READDATAWIDTHA = 3'b000; - end else if (CFG_DBITS == 2) begin - assign WRITEDATAWIDTHB = 3'b001; - assign READDATAWIDTHA = 3'b001; - end else if (CFG_DBITS > 2 && CFG_DBITS <= 4) begin - assign WRITEDATAWIDTHB = 3'b010; - assign READDATAWIDTHA = 3'b010; - end else if (CFG_DBITS > 4 && CFG_DBITS <= 9) begin - assign WRITEDATAWIDTHB = 3'b011; - assign READDATAWIDTHA = 3'b011; - end else if (CFG_DBITS > 9 && CFG_DBITS <= 18) begin - assign WRITEDATAWIDTHB = 3'b100; - assign READDATAWIDTHA = 3'b100; - end else if (CFG_DBITS > 18 && CFG_DBITS <= 36) begin - assign WRITEDATAWIDTHB = 3'b101; - assign READDATAWIDTHA = 3'b101; - end*/ - generate if (CFG_DBITS > 8) begin - TDP_BRAM36 #( - //`include "brams_init_36.vh" - .READ_WIDTH_A(CFG_DBITS), - .READ_WIDTH_B(CFG_DBITS), - .WRITE_WIDTH_A(CFG_DBITS), - .WRITE_WIDTH_B(CFG_DBITS), - ) _TECHMAP_REPLACE_ ( - .WRITEDATAA(32'hFFFFFFFF), - .WRITEDATAAP(4'hF), - .READDATAA(DO[31:0]), - .READDATAAP(DOP[3:0]), - .ADDRA(A1ADDR_15), - .CLOCKA(CLK2), - .READENABLEA(A1EN), - .WRITEENABLEA(1'b0), - .BYTEENABLEA(4'b0), - //.WRITEDATAWIDTHA(3'b0), - //.READDATAWIDTHA(READDATAWIDTHA), + wire [14:CFG_ABITS] A1ADDR_CMPL = {15-CFG_ABITS{1'b0}}; + wire [14:CFG_ABITS] B1ADDR_CMPL = {15-CFG_ABITS{1'b0}}; + wire [14:CFG_ABITS] C1ADDR_CMPL = {15-CFG_ABITS{1'b0}}; + wire [14:CFG_ABITS] D1ADDR_CMPL = {15-CFG_ABITS{1'b0}}; - .WRITEDATAB(DI), - .WRITEDATABP(DIP), - .READDATAB(DOBDO), - .READDATABP(DOPBDOP), - .ADDRB(B1ADDR_15), - .CLOCKB(CLK3), - .READENABLEA(1'b0), - .WRITEENABLEB(1'b1), - .BYTEENABLEB(B1EN) - //.WRITEDATAWIDTHB(WRITEDATAWIDTHB), - //.READDATAWIDTHB(3'b0) - ); - end else begin - TDP_BRAM36 #( - //`include "brams_init_32.vh" - ) _TECHMAP_REPLACE_ ( - .WRITEDATAA(32'hFFFFFFFF), - .WRITEDATAAP(4'hF), - .READDATAA(DO[31:0]), - .READDATAAP(DOP[3:0]), - .ADDRA(A1ADDR_15), - .CLOCKA(CLK2), - .READENABLEA(A1EN), - .WRITEENABLEA(1'b0), - .BYTEENABLEA(4'b0), - //.WRITEDATAWIDTHA(3'b0), - //.READDATAWIDTHA(READDATAWIDTHA), + wire [14:0] A1ADDR_TOTAL = {A1ADDR_CMPL, A1ADDR}; + wire [14:0] B1ADDR_TOTAL = {B1ADDR_CMPL, B1ADDR}; + wire [14:0] C1ADDR_TOTAL = {C1ADDR_CMPL, C1ADDR}; + wire [14:0] D1ADDR_TOTAL = {D1ADDR_CMPL, D1ADDR}; - .WRITEDATAB(DI), - .WRITEDATABP(DIP), - .READDATAB(DOBDO), - .READDATABP(DOPBDOP), - .ADDRB(B1ADDR_15), - .CLOCKB(CLK3), - .READENABLEB(1'b0), - .WRITEENABLEB(1'b1), - .BYTEENABLEB(B1EN) - //.WRITEDATAWIDTHB(WRITEDATAWIDTHB), - //.READDATAWIDTHB(3'b0) - ); - end endgenerate + wire [35:CFG_DBITS] A1DATA_CMPL; + wire [35:CFG_DBITS] C1DATA_CMPL; + + wire [35:0] A1DATA_TOTAL = {A1DATA_CMPL, A1DATA}; + wire [35:0] C1DATA_TOTAL = {C1DATA_CMPL, C1DATA}; + + wire [14:0] PORT_A_ADDR; + wire [14:0] PORT_B_ADDR; + + case (CFG_DBITS) + 1: begin + assign PORT_A_ADDR = A1EN ? A1ADDR_TOTAL : (B1EN ? B1ADDR_TOTAL : 15'd0); + assign PORT_B_ADDR = C1EN ? C1ADDR_TOTAL : (D1EN ? D1ADDR_TOTAL : 15'd0); + assign WMODE = MODE_1; + assign RMODE = MODE_1; + end + + 2: begin + assign PORT_A_ADDR = A1EN ? (A1ADDR_TOTAL << 1) : (B1EN ? (B1ADDR_TOTAL << 1) : 15'd0); + assign PORT_B_ADDR = C1EN ? (C1ADDR_TOTAL << 1) : (D1EN ? (D1ADDR_TOTAL << 1) : 15'd0); + assign WMODE = MODE_2; + assign RMODE = MODE_2; + end + + 4: begin + assign PORT_A_ADDR = A1EN ? (A1ADDR_TOTAL << 5) : (B1EN ? (B1ADDR_TOTAL << 5) : 15'd0); + assign PORT_B_ADDR = C1EN ? (C1ADDR_TOTAL << 5) : (D1EN ? (D1ADDR_TOTAL << 5) : 15'd0); + assign WMODE = MODE_4; + assign RMODE = MODE_4; + end + + 8: begin + assign PORT_A_ADDR = A1EN ? (A1ADDR_TOTAL << 3) : (B1EN ? (B1ADDR_TOTAL << 3) : 15'd0); + assign PORT_B_ADDR = C1EN ? (C1ADDR_TOTAL << 3) : (D1EN ? (D1ADDR_TOTAL << 3) : 15'd0); + assign WMODE = MODE_9; + assign RMODE = MODE_9; + end + + 9: begin + assign PORT_A_ADDR = A1EN ? (A1ADDR_TOTAL << 3) : (B1EN ? (B1ADDR_TOTAL << 3) : 15'd0); + assign PORT_B_ADDR = C1EN ? (C1ADDR_TOTAL << 3) : (D1EN ? (D1ADDR_TOTAL << 3) : 15'd0); + assign WMODE = MODE_9; + assign RMODE = MODE_9; + end + + 16: begin + assign PORT_A_ADDR = A1EN ? (A1ADDR_TOTAL << 4) : (B1EN ? (B1ADDR_TOTAL << 4) : 15'd0); + assign PORT_B_ADDR = C1EN ? (C1ADDR_TOTAL << 4) : (D1EN ? (D1ADDR_TOTAL << 4) : 15'd0); + assign WMODE = MODE_18; + assign RMODE = MODE_18; + end + + 18: begin + assign PORT_A_ADDR = A1EN ? (A1ADDR_TOTAL << 4) : (B1EN ? (B1ADDR_TOTAL << 4) : 15'd0); + assign PORT_B_ADDR = C1EN ? (C1ADDR_TOTAL << 4) : (D1EN ? (D1ADDR_TOTAL << 4) : 15'd0); + assign WMODE = MODE_18; + assign RMODE = MODE_18; + end + + 32: begin + assign PORT_A_ADDR = A1EN ? (A1ADDR_TOTAL << 5) : (B1EN ? (B1ADDR_TOTAL << 5) : 15'd0); + assign PORT_B_ADDR = C1EN ? (C1ADDR_TOTAL << 5) : (D1EN ? (D1ADDR_TOTAL << 5) : 15'd0); + assign WMODE = MODE_36; + assign RMODE = MODE_36; + end + 36: begin + assign PORT_A_ADDR = A1EN ? (A1ADDR_TOTAL << 5) : (B1EN ? (B1ADDR_TOTAL << 5) : 15'd0); + assign PORT_B_ADDR = C1EN ? (C1ADDR_TOTAL << 5) : (D1EN ? (D1ADDR_TOTAL << 5) : 15'd0); + assign WMODE = MODE_36; + assign RMODE = MODE_36; + end + default: begin + assign PORT_A_ADDR = A1EN ? A1ADDR_TOTAL : (B1EN ? B1ADDR_TOTAL : 15'd0); + assign PORT_B_ADDR = C1EN ? C1ADDR_TOTAL : (D1EN ? D1ADDR_TOTAL : 15'd0); + assign WMODE = MODE_36; + assign RMODE = MODE_36; + end + endcase + + + assign SPLIT = 1'b0; + assign FLUSH1 = 1'b0; + assign FLUSH2 = 1'b0; + assign UPAE1 = 11'd10; + assign UPAF1 = 11'd10; + assign UPAE2 = 11'd10; + assign UPAF2 = 11'd10; + assign SYNC_FIFO1 = 1'b0; + assign SYNC_FIFO2 = 1'b0; + assign FMODE1 = 1'b0; + assign FMODE2 = 1'b0; + assign POWERDN1 = 1'b0; + assign POWERDN2 = 1'b0; + assign SLEEP1 = 1'b0; + assign SLEEP2 = 1'b0; + assign PROTECT1 = 1'b0; + assign PROTECT2 = 1'b0; + assign RAM_ID_i = 9'b0; + + assign PL_INIT_i = 1'b0; + assign PL_ENA_i = 1'b0; + assign PL_REN_i = 1'b0; + assign PL_CLK_i = 1'b0; + assign PL_WEN_i = 2'b0; + assign PL_ADDR_i = 24'b0; + assign PL_DATA_i = 36'b0; + + TDP_BRAM36 #() _TECHMAP_REPLACE_ ( + .WMODE_A1_i(WMODE), + .WMODE_A2_i(WMODE), + .RMODE_A1_i(RMODE), + .RMODE_A2_i(RMODE), + + .WDATA_A1_i(B1DATA[17:0]), + .WDATA_A2_i(B1DATA[35:18]), + .RDATA_A1_o(A1DATA_TOTAL[17:0]), + .RDATA_A2_o(A1DATA_TOTAL[35:18]), + .ADDR_A1_i(PORT_A_ADDR), + .ADDR_A2_i(PORT_A_ADDR), + .CLK_A1_i(CLK1), + .CLK_A2_i(CLK1), + .REN_A1_i(A1EN), + .REN_A2_i(A1EN), + .WEN_A1_i(B1EN[0]), + .WEN_A2_i(B1EN[0]), + .BE_A1_i({B1EN[1],B1EN[0]}), + .BE_A2_i({B1EN[3],B1EN[2]}), + + + .WMODE_B1_i(WMODE), + .WMODE_B2_i(WMODE), + .RMODE_B1_i(RMODE), + .RMODE_B2_i(RMODE), + + .WDATA_B1_i(D1DATA[17:0]), + .WDATA_B2_i(D1DATA[35:18]), + .RDATA_B1_o(C1DATA_TOTAL[17:0]), + .RDATA_B2_o(C1DATA_TOTAL[35:18]), + .ADDR_B1_i(PORT_B_ADDR), + .ADDR_B2_i(PORT_B_ADDR), + .CLK_B1_i(CLK2), + .CLK_B2_i(CLK2), + .REN_B1_i(C1EN), + .REN_B2_i(C1EN), + .WEN_B1_i(D1EN[0]), + .WEN_B2_i(D1EN[0]), + .BE_B1_i({D1EN[1],D1EN[0]}), + .BE_B2_i({D1EN[3],D1EN[2]}), + + + .SPLIT_i(SPLIT), + .FLUSH1_i(FLUSH1), + .FLUSH2_i(FLUSH2), + .UPAE1_i(UPAE1), + .UPAF1_i(UPAF1), + .UPAE2_i(UPAE2), + .UPAF2_i(UPAF2), + .SYNC_FIFO1_i(SYNC_FIFO1), + .SYNC_FIFO2_i(SYNC_FIFO2), + .FMODE1_i(FMODE1), + .FMODE2_i(FMODE2), + .POWERDN1_i(POWERDN1), + .POWERDN2_i(POWERDN2), + .SLEEP1_i(SLEEP1), + .SLEEP2_i(SLEEP2), + .PROTECT1_i(PROTECT1), + .PROTECT2_i(PROTECT2), + .RAM_ID_i(RAM_ID_i), + + .PL_INIT_i(PL_INIT_i), + .PL_ENA_i(PL_ENA_i), + .PL_WEN_i(PL_WEN_i), + .PL_REN_i(PL_REN_i), + .PL_CLK_i(PL_CLK_i), + .PL_ADDR_i(PL_ADDR_i), + .PL_DATA_i(PL_DATA_i), + .PL_INIT_o(PL_INIT_o), + .PL_ENA_o(PL_ENA_o), + .PL_WEN_o(PL_WEN_o), + .PL_REN_o(PL_REN_o), + .PL_CLK_o(PL_CLK_o), + .PL_ADDR_o(), + .PL_DATA_o(PL_DATA_o) + + ); endmodule // ------------------------------------------------------------------------