ql-qlf: qlf_k6n10f: bram: introduce TDP synthesis test cases Signed-off-by: Paweł Czarnecki <pczarnecki@antmicro.com>
diff --git a/ql-qlf-plugin/tests/Makefile b/ql-qlf-plugin/tests/Makefile index 77938e3..fef6c31 100644 --- a/ql-qlf-plugin/tests/Makefile +++ b/ql-qlf-plugin/tests/Makefile
@@ -23,7 +23,8 @@ pp3_bram \ qlf_k6n10f/dsp_mult \ qlf_k6n10f/dsp_simd \ - qlf_k6n10f/dsp_macc + qlf_k6n10f/dsp_macc \ + qlf_k6n10f/bram_tdp # qlf_k6n10_bram \ SIM_TESTS = \ @@ -49,4 +50,5 @@ qlf_k6n10f-dsp_mult_verify = true qlf_k6n10f-dsp_simd_verify = true qlf_k6n10f-dsp_macc_verify = true +qlf_k6n10f-bram_tdp_verify = true #qlf_k6n10_bram_verify = true
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram_tdp/bram_tdp.tcl b/ql-qlf-plugin/tests/qlf_k6n10f/bram_tdp/bram_tdp.tcl new file mode 100644 index 0000000..d304fa5 --- /dev/null +++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram_tdp/bram_tdp.tcl
@@ -0,0 +1,50 @@ +yosys -import + +if { [info procs ql-qlf-k6n10f] == {} } { plugin -i ql-qlf } +yosys -import ; + +read_verilog $::env(DESIGN_TOP).v +design -save bram_tdp + +select BRAM_TDP_32x512 +select * +synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_32x512 +opt_expr -undriven +opt_clean +stat +write_verilog bram_tdp_32x512_synth.v +select -assert-count 1 t:TDP_BRAM36 + +select -clear +design -load bram_tdp +select BRAM_TDP_16x1024 +select * +synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_16x1024 +opt_expr -undriven +opt_clean +stat +write_verilog bram_tdp_16x1024_synth.v +select -assert-count 1 t:TDP_BRAM36 + +select -clear +design -load bram_tdp +select BRAM_TDP_8x2048 +select * +synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_8x2048 +opt_expr -undriven +opt_clean +stat +write_verilog bram_tdp_8x2048_synth.v +select -assert-count 1 t:TDP_BRAM36 + +select -clear +design -load bram_tdp +select BRAM_TDP_4x4096 +select * +synth_quicklogic -family qlf_k6n10f -top BRAM_TDP_4x4096 +opt_expr -undriven +opt_clean +stat +write_verilog bram_tdp_4x4096_synth.v +select -assert-count 1 t:TDP_BRAM36 +
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram_tdp/bram_tdp.v b/ql-qlf-plugin/tests/qlf_k6n10f/bram_tdp/bram_tdp.v new file mode 100644 index 0000000..3486fa2 --- /dev/null +++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram_tdp/bram_tdp.v
@@ -0,0 +1,284 @@ +// Copyright (C) 2022 The SymbiFlow Authors. +// +// Use of this source code is governed by a ISC-style +// license that can be found in the LICENSE file or at +// https://opensource.org/licenses/ISC +// +// SPDX-License-Identifier:ISC + +module BRAM_TDP #(parameter AWIDTH = 9, +parameter DWIDTH = 32)( + clk_a, + rce_a, + ra_a, + rq_a, + wce_a, + wa_a, + wd_a, + + clk_b, + rce_b, + ra_b, + rq_b, + wce_b, + wa_b, + wd_b +); + + input clk_a; + input rce_a; + input [AWIDTH-1:0] ra_a; + output reg [DWIDTH-1:0] rq_a; + input wce_a; + input [AWIDTH-1:0] wa_a; + input [DWIDTH-1:0] wd_a; + + input clk_b; + input rce_b; + input [AWIDTH-1:0] ra_b; + output reg [DWIDTH-1:0] rq_b; + input wce_b; + input [AWIDTH-1:0] wa_b; + input [DWIDTH-1:0] wd_b; + + reg [DWIDTH-1:0] memory[0:(1<<AWIDTH)-1]; + + always @(posedge clk_a) begin + if (rce_a) + rq_a <= memory[ra_a]; + + if (wce_a) + memory[wa_a] <= wd_a; + end + + always @(posedge clk_b) begin + if (rce_b) + rq_b <= memory[ra_b]; + + if (wce_b) + memory[wa_b] <= wd_b; + end + + integer i; + initial + begin + for(i = 0; i < (1<<AWIDTH)-1; i = i + 1) + memory[i] = 0; + end + +endmodule + +module BRAM_TDP_32x512( + clk_a, + rce_a, + ra_a, + rq_a, + wce_a, + wa_a, + wd_a, + + clk_b, + rce_b, + ra_b, + rq_b, + wce_b, + wa_b, + wd_b +); + +parameter AWIDTH = 9; +parameter DWIDTH = 32; + + input clk_a; + input rce_a; + input [AWIDTH-1:0] ra_a; + output [DWIDTH-1:0] rq_a; + input wce_a; + input [AWIDTH-1:0] wa_a; + input [DWIDTH-1:0] wd_a; + input clk_b; + input rce_b; + input [AWIDTH-1:0] ra_b; + output [DWIDTH-1:0] rq_b; + input wce_b; + input [AWIDTH-1:0] wa_b; + input [DWIDTH-1:0] wd_b; + +BRAM_TDP #(.AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) + BRAM_TDP_32x512 (.clk_a(clk_a), + .rce_a(rce_a), + .ra_a(ra_a), + .rq_a(rq_a), + .wce_a(wce_a), + .wa_a(wa_a), + .wd_a(wd_a), + .clk_b(clk_b), + .rce_b(rce_b), + .ra_b(ra_b), + .rq_b(rq_b), + .wce_b(wce_b), + .wa_b(wa_b), + .wd_b(wd_b)); + +endmodule + +module BRAM_TDP_16x1024( + clk_a, + rce_a, + ra_a, + rq_a, + wce_a, + wa_a, + wd_a, + clk_b, + rce_b, + ra_b, + rq_b, + wce_b, + wa_b, + wd_b +); + +parameter AWIDTH = 10; +parameter DWIDTH = 16; + + input clk_a; + input rce_a; + input [AWIDTH-1:0] ra_a; + output [DWIDTH-1:0] rq_a; + input wce_a; + input [AWIDTH-1:0] wa_a; + input [DWIDTH-1:0] wd_a; + + input clk_b; + input rce_b; + input [AWIDTH-1:0] ra_b; + output [DWIDTH-1:0] rq_b; + input wce_b; + input [AWIDTH-1:0] wa_b; + input [DWIDTH-1:0] wd_b; + +BRAM_TDP #(.AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) + BRAM_TDP_16x1024 (.clk_a(clk_a), + .rce_a(rce_a), + .ra_a(ra_a), + .rq_a(rq_a), + .wce_a(wce_a), + .wa_a(wa_a), + .wd_a(wd_a), + .clk_b(clk_b), + .rce_b(rce_b), + .ra_b(ra_b), + .rq_b(rq_b), + .wce_b(wce_b), + .wa_b(wa_b), + .wd_b(wd_b)); +endmodule + +module BRAM_TDP_8x2048( + clk_a, + rce_a, + ra_a, + rq_a, + wce_a, + wa_a, + wd_a, + + clk_b, + rce_b, + ra_b, + rq_b, + wce_b, + wa_b, + wd_b +); + +parameter AWIDTH = 11; +parameter DWIDTH = 8; + + input clk_a; + input rce_a; + input [AWIDTH-1:0] ra_a; + output [DWIDTH-1:0] rq_a; + input wce_a; + input [AWIDTH-1:0] wa_a; + input [DWIDTH-1:0] wd_a; + + input clk_b; + input rce_b; + input [AWIDTH-1:0] ra_b; + output [DWIDTH-1:0] rq_b; + input wce_b; + input [AWIDTH-1:0] wa_b; + input [DWIDTH-1:0] wd_b; + +BRAM_TDP #(.AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) + BRAM_TDP_8x2048 (.clk_a(clk_a), + .rce_a(rce_a), + .ra_a(ra_a), + .rq_a(rq_a), + .wce_a(wce_a), + .wa_a(wa_a), + .wd_a(wd_a), + .clk_b(clk_b), + .rce_b(rce_b), + .ra_b(ra_b), + .rq_b(rq_b), + .wce_b(wce_b), + .wa_b(wa_b), + .wd_b(wd_b)); +endmodule + +module BRAM_TDP_4x4096( + clk_a, + rce_a, + ra_a, + rq_a, + wce_a, + wa_a, + wd_a, + + clk_b, + rce_b, + ra_b, + rq_b, + wce_b, + wa_b, + wd_b +); + +parameter AWIDTH = 12; +parameter DWIDTH = 4; + + input clk_a; + input rce_a; + input [AWIDTH-1:0] ra_a; + output [DWIDTH-1:0] rq_a; + input wce_a; + input [AWIDTH-1:0] wa_a; + input [DWIDTH-1:0] wd_a; + + input clk_b; + input rce_b; + input [AWIDTH-1:0] ra_b; + output [DWIDTH-1:0] rq_b; + input wce_b; + input [AWIDTH-1:0] wa_b; + input [DWIDTH-1:0] wd_b; + +BRAM_TDP #(.AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) + BRAM_TDP_4x4096 (.clk_a(clk_a), + .rce_a(rce_a), + .ra_a(ra_a), + .rq_a(rq_a), + .wce_a(wce_a), + .wa_a(wa_a), + .wd_a(wd_a), + .clk_b(clk_b), + .rce_b(rce_b), + .ra_b(ra_b), + .rq_b(rq_b), + .wce_b(wce_b), + .wa_b(wa_b), + .wd_b(wd_b)); +endmodule