SDC: Add dangling wires to PLL design

Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>

sdc-plugin/tests/pll/pll.v

diff --git a/sdc-plugin/tests/pll/pll.v b/sdc-plugin/tests/pll/pll.v
index 63542da..5c401b8 100644
--- a/sdc-plugin/tests/pll/pll.v
+++ b/sdc-plugin/tests/pll/pll.v
@@ -46,6 +46,8 @@
 	.CLKOUT0(main_clkout0),
 	.CLKOUT1(main_clkout1),
 	.CLKOUT2(main_clkout2),
+	.CLKOUT3(main_clkout3),
+	.CLKOUT4(main_clkout4),
 	.LOCKED(main_locked)
 );