Support `longint` typespec

Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>

systemverilog-plugin/UhdmAst.cc

diff --git a/systemverilog-plugin/UhdmAst.cc b/systemverilog-plugin/UhdmAst.cc
index 9ed5156..62f7d67 100644
--- a/systemverilog-plugin/UhdmAst.cc
+++ b/systemverilog-plugin/UhdmAst.cc
@@ -3427,6 +3427,16 @@
     current_node->is_signed = true;
 }
 
+void UhdmAst::process_longint_typespec()
+{
+    std::vector<AST::AstNode *> packed_ranges;   // comes before wire name
+    std::vector<AST::AstNode *> unpacked_ranges; // comes after wire name
+    current_node = make_ast_node(AST::AST_WIRE);
+    packed_ranges.push_back(make_range(63, 0));
+    add_multirange_wire(current_node, packed_ranges, unpacked_ranges);
+    current_node->is_signed = true;
+}
+
 void UhdmAst::process_byte_typespec()
 {
     std::vector<AST::AstNode *> packed_ranges;   // comes before wire name
@@ -3616,6 +3626,7 @@
         case vpiUnionVar:
         case vpiEnumVar:
         case vpiShortIntVar:
+        case vpiLongIntVar:
         case vpiIntVar:
         case vpiIntegerVar:
             break;
@@ -4098,6 +4109,9 @@
     case vpiShortIntTypespec:
         process_shortint_typespec();
         break;
+    case vpiLongIntTypespec:
+        process_longint_typespec();
+        break;
     case vpiTimeTypespec:
         process_time_typespec();
         break;

systemverilog-plugin/UhdmAst.h

diff --git a/systemverilog-plugin/UhdmAst.h b/systemverilog-plugin/UhdmAst.h
index cc84979..af0b808 100644
--- a/systemverilog-plugin/UhdmAst.h
+++ b/systemverilog-plugin/UhdmAst.h
@@ -127,6 +127,7 @@
     void process_logic_typespec();
     void process_int_typespec();
     void process_shortint_typespec();
+    void process_longint_typespec();
     void process_time_typespec();
     void process_bit_typespec();
     void process_string_var();