| commit | dfe9b1a15b494e7dd81a2b394dac30ea707ec5cc | [log] [tgz] |
|---|---|---|
| author | Karol Gugala <kgugala@antmicro.com> | Tue Jan 23 17:14:54 2024 +0100 |
| committer | GitHub <noreply@github.com> | Tue Jan 23 17:14:54 2024 +0100 |
| tree | 666f05a6d65572468105da4e3e32a128b9353f75 | |
| parent | 90fdbc4426f1c29dac6262589eeaddcd41e1be85 [diff] |
README: update synlig path
diff --git a/README.md b/README.md index d440eae..12700e0 100644 --- a/README.md +++ b/README.md
@@ -99,7 +99,7 @@ ## SystemVerilog plugin -The SystemVerilog plugin has been moved to [chipsalliance/systemverilog-plugin](https://github.com/chipsalliance/systemverilog-plugin). +The SystemVerilog plugin has been moved to [chipsalliance/synlig](https://github.com/chipsalliance/synlig). ## Clock Gating plugin