| commit | d960817d8072e9e134fa13e03180d3911e1099c5 | [log] [tgz] |
|---|---|---|
| author | Tomasz Michalak <tmichalak@antmicro.com> | Mon Mar 09 10:01:25 2020 +0100 |
| committer | Tomasz Michalak <tmichalak@antmicro.com> | Mon Mar 09 10:35:36 2020 +0100 |
| tree | 3e56a34d4aa47f433be0025db6f4300486c90fc6 | |
| parent | 450aca4e581179128e439f08f58d95c0c84b416e [diff] |
minitests: Copy modules to work around Yosys bugs Yosys is unable to infer OBUFTs when they are instantiated in submodule, neither does it handle inference of RAMB36 TDP if 2 port memories are instantiated in the same verilog module. Both issues have been reported: https://github.com/YosysHQ/yosys/issues/1737 https://github.com/YosysHQ/yosys/issues/1748 Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Project U-Ray is an attempt at documenting the bitstream format for the Xilinx Ultrascale and Ultrascale+ parts including all parts from the following lines;
It takes a lot of the learning from Project X-Ray and Project Trellis.
| Board | Maker | Price | Part |
|---|---|---|---|
| Ultra96-V2 Zynq UltraScale+ ZU3EG Development Board (ULTRA96-V2-G) | ??? | Xilinx Zynq UltraScale+ MPSoC ZU3EG | $USD249 |
| Genesys ZU: Zynq Ultrascale+ MPSoC Development Board | Digilent | Xilinx Zynq UltraScale+ MPSoC ZU3EG | $USD1,149 |
We have a goal of initially targeting parts supported by WebPack so that anyone can contribute.
WebPack supports the following parts;
Zynq UltraScale+ MPSoC -- UltraScale+ MPSoC