spec/rclk_int.py

# Copyright 2020 Project U-Ray Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#      http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.

import numpy as np
import sys

N = 5000

bufgces = []
with open(sys.argv[1], "r") as tf:
	for line in tf:
		sl = line.strip().split(",")
		if len(sl) < 4:
			continue
		for site in sl[4:]:
			if "BUFGCE" in site and "HDIO" not in site:
				bufgces.append(site.split(":")[0])

print("module layer_1(input [31:0] clk, input [71:0] cen, input d, output q);")
print("    wire [%d:0] r;" % N)
print("    assign r[0] = d;")
print("    assign q = r[%d];" % N)
print()
for i in range(N):
	print("    FDCE ff_%d (.C(clk[%d]), .CLR(1'b0), .CE(cen[%d]), .D(r[%d]), .Q(r[%d]));" % (i, (i * 32) // N, np.random.randint(72), i, i+1))
	print()
print("endmodule")


M = 16
print("module top(input [15:0] clk, cen, input d, output q);")
print("    wire [511:0] clk_int;")
print("    wire [71:0] cen_int;")
print("    assign clk_int[15:0] = clk;")
print("    assign cen_int[15:0] = cen;")
print("    assign cen_int[71:64] = 8'hFF;")
for i in range(16, 512):
	a = np.random.randint(16)
	b = None
	while b is None or b == a:
		b = np.random.randint(16)
	c = None
	while c is None or c == a or c == b:
		c = np.random.randint(16)
	bg = None
	if len(bufgces) > 0:
		bg = bufgces.pop()
	if bg is not None and np.random.randint(3) > 0:
		if "DIV" in bg:
			print("    BUFGCE_DIV #(.BUFGCE_DIVIDE(3)) bufg_%d (.I(clk[%d] ^ clk[%d] ^ clk[%d]), .CLR(0), .CE(1'b1), .O(clk_int[%d]));" % (i, a, b, c, i))
		else:
			print("    BUFGCE bufg_%d (.I(clk[%d] ^ clk[%d] ^ clk[%d]), .CE(1'b1), .O(clk_int[%d]));" % (i, a, b, c, i))
	else:
		print("    assign clk_int[%d] = clk[%d] ^ clk[%d] ^ clk[%d];" % (i, a, b, c))
	if i < 64:
		print("    assign cen_int[%d] = cen[%d] ^ cen[%d];" % (i, a, b))
print()
print("    wire [%d:0] r;" % M)
print("    assign r[0] = d;")
print("    assign q = r[%d];" % M)
for i in range(M):
	print("    layer_1 submod_%d(.clk(clk_int[%d +: 32]), .cen(cen_int), .d(r[%d]), .q(r[%d]));" % (i, 32 * i, i, i+1))
print("endmodule")