Fix underline length Signed-off-by: Daniel Lim Wee Soong <weesoong.lim@gmail.com>
diff --git a/docs/examples.rst b/docs/examples.rst index 1978003..158bdd3 100644 --- a/docs/examples.rst +++ b/docs/examples.rst
@@ -1,5 +1,5 @@ Examples -============ +======== Here we have examples on how v2x converts a Verilog module to its corresponding model.xml and pb_type.xml files. These examples are taken from the `v2x test cases <https://github.com/SymbiFlow/python-symbiflow-v2x/tree/master/tests>`_.
diff --git a/docs/examples/clocks.rst b/docs/examples/clocks.rst index c596af1..fc6adc5 100644 --- a/docs/examples/clocks.rst +++ b/docs/examples/clocks.rst
@@ -1,7 +1,7 @@ .. Clock Example Tests Clock -============== +===== There are various ways for an input or output port to be detected as a clock by v2x. Here are examples on ways to do so.
diff --git a/docs/examples/clocks/autodetection.rst b/docs/examples/clocks/autodetection.rst index 3c0bd24..789cf52 100644 --- a/docs/examples/clocks/autodetection.rst +++ b/docs/examples/clocks/autodetection.rst
@@ -1,5 +1,5 @@ Autodetection of clock from flipflop -===================================== +==================================== .. include:: ../../../tests/clocks/dff_one_clock/README.rst .. include:: ../../../tests/clocks/dff_comb_one_clock/README.rst
diff --git a/docs/examples/clocks/manual_input.rst b/docs/examples/clocks/manual_input.rst index 994d15a..a5d6b39 100644 --- a/docs/examples/clocks/manual_input.rst +++ b/docs/examples/clocks/manual_input.rst
@@ -1,5 +1,5 @@ Manually set inputs as clock -================================== +============================ .. include:: ../../../tests/clocks/input_attr_clock/README.rst .. include:: ../../../tests/clocks/input_attr_not_clock/README.rst
diff --git a/docs/examples/clocks/manual_output.rst b/docs/examples/clocks/manual_output.rst index cfb98fe..39e7894 100644 --- a/docs/examples/clocks/manual_output.rst +++ b/docs/examples/clocks/manual_output.rst
@@ -1,5 +1,5 @@ Manually set outputs as clock -================================== +============================= .. include:: ../../../tests/clocks/output_attr_clock/README.rst .. include:: ../../../tests/clocks/output_named_clk/README.rst
diff --git a/docs/examples/clocks/multiple.rst b/docs/examples/clocks/multiple.rst index 29677c6..596ad4b 100644 --- a/docs/examples/clocks/multiple.rst +++ b/docs/examples/clocks/multiple.rst
@@ -1,5 +1,5 @@ Multiple clocks -================================== +=============== .. include:: ../../../tests/clocks/multiple_inputs_named_clk/README.rst .. include:: ../../../tests/clocks/multiple_outputs_named_clk/README.rst
diff --git a/docs/examples/dsp.rst b/docs/examples/dsp.rst index 7bc7e39..408007b 100644 --- a/docs/examples/dsp.rst +++ b/docs/examples/dsp.rst
@@ -1,7 +1,7 @@ .. DSP Based Example Tests DSP -============ +=== .. toctree::
diff --git a/docs/examples/vtr-examples.rst b/docs/examples/vtr-examples.rst index 98c0b22..aef1d74 100644 --- a/docs/examples/vtr-examples.rst +++ b/docs/examples/vtr-examples.rst
@@ -1,7 +1,7 @@ .. Examples from the Verilog to Routing documentation / tutorials. Verilog to Routing -=========================== +================== Primitive Block Timing Modeling Tutorial ----------------------------------------
diff --git a/tests/clocks/dff_one_clock/README.rst b/tests/clocks/dff_one_clock/README.rst index 35a7605..4acbb70 100644 --- a/tests/clocks/dff_one_clock/README.rst +++ b/tests/clocks/dff_one_clock/README.rst
@@ -1,5 +1,5 @@ D-Flipflop with one clock -+++++++++++++++++++++++++++++++++++ ++++++++++++++++++++++++++ The following shows a simple D-flip flop driven by one clock. ``input wire a`` should be detected as a clock because it drives the flip flop.
diff --git a/tests/clocks/dff_two_clocks/README.rst b/tests/clocks/dff_two_clocks/README.rst index 9925ebe..86a9fa7 100644 --- a/tests/clocks/dff_two_clocks/README.rst +++ b/tests/clocks/dff_two_clocks/README.rst
@@ -1,5 +1,5 @@ D-Flipflop with two clocks -+++++++++++++++++++++++++++++++++++ +++++++++++++++++++++++++++ ``input wire c1`` and ``input wire c2`` should be detected as clocks because they drive the flip flop.
diff --git a/tests/clocks/input_attr_clock/README.rst b/tests/clocks/input_attr_clock/README.rst index 3b34332..792c0ff 100644 --- a/tests/clocks/input_attr_clock/README.rst +++ b/tests/clocks/input_attr_clock/README.rst
@@ -1,5 +1,5 @@ Manually set input as clock by setting the CLOCK attribute -+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ The following shows that ``input wire a`` is given the ``(* CLOCK *)`` attribute.
diff --git a/tests/clocks/input_attr_not_clock/README.rst b/tests/clocks/input_attr_not_clock/README.rst index 93fa457..b2404e1 100644 --- a/tests/clocks/input_attr_not_clock/README.rst +++ b/tests/clocks/input_attr_not_clock/README.rst
@@ -1,5 +1,5 @@ Force input as regular input by setting the CLOCK attribute -++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ``input wire a`` should be detected as a clock because it drives the flip flop. However, it has the attribute CLOCK set to 0 which should force it to be a regular input.
diff --git a/tests/clocks/input_named_clk/README.rst b/tests/clocks/input_named_clk/README.rst index ed03902..ef83375 100644 --- a/tests/clocks/input_named_clk/README.rst +++ b/tests/clocks/input_named_clk/README.rst
@@ -1,5 +1,5 @@ Set input as clock by name (clk) -+++++++++++++++++++++++++++++++++++ +++++++++++++++++++++++++++++++++ An input wire can be set as a clock by assigning ``clk`` as its name.
diff --git a/tests/clocks/input_named_regex/README.rst b/tests/clocks/input_named_regex/README.rst index 6cad83f..fd46a7b 100644 --- a/tests/clocks/input_named_regex/README.rst +++ b/tests/clocks/input_named_regex/README.rst
@@ -1,5 +1,5 @@ Set input as clock by name (regex) -+++++++++++++++++++++++++++++++++++ +++++++++++++++++++++++++++++++++++ An input wire can be set as a clock by having ``clk`` in its name (case insensitive).
diff --git a/tests/clocks/multiple_outputs_named_clk/README.rst b/tests/clocks/multiple_outputs_named_clk/README.rst index 0489f6e..fc00979 100644 --- a/tests/clocks/multiple_outputs_named_clk/README.rst +++ b/tests/clocks/multiple_outputs_named_clk/README.rst
@@ -1,5 +1,5 @@ Set outputs as clock by name (multiple clock outputs) -++++++++++++++++++++++++++++++++++++++++++++++++++++++ ++++++++++++++++++++++++++++++++++++++++++++++++++++++ ``output wire rdclk`` and ``output wire wrclk`` have ``clk`` in their names, hence are recognized as clock inputs by v2x.
diff --git a/tests/clocks/output_attr_clock/README.rst b/tests/clocks/output_attr_clock/README.rst index b8224e2..7e8b221 100644 --- a/tests/clocks/output_attr_clock/README.rst +++ b/tests/clocks/output_attr_clock/README.rst
@@ -1,5 +1,5 @@ Manually set output as clock by setting the CLOCK attribute -++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ The following shows that ``output wire o`` is given the ``(* CLOCK *)`` attribute.
diff --git a/tests/clocks/output_named_clk/README.rst b/tests/clocks/output_named_clk/README.rst index 61df9d7..f859e8b 100644 --- a/tests/clocks/output_named_clk/README.rst +++ b/tests/clocks/output_named_clk/README.rst
@@ -1,5 +1,5 @@ Set output as clock by name (clk) -+++++++++++++++++++++++++++++++++++ ++++++++++++++++++++++++++++++++++ An output wire can be set as a clock by assigning ``clk`` as its name.