Added test. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

diff --git a/tests/net_attr/README.md b/tests/net_attr/README.md
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--- /dev/null
+++ b/tests/net_attr/README.md

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+# Test for multiple occurrence of the same numerical net id in the "netnames" list.
+
+When connecting a singal through multiple wires Yosys assigns name of each of them to the same net id. Such a case triggered a bug in V2X causing it to crash. This test verifies that the reworked handling of "netnames" in V2X behaves properly.

diff --git a/tests/net_attr/child/child.model.xml b/tests/net_attr/child/child.model.xml
new file mode 100644
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+++ b/tests/net_attr/child/child.model.xml

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+<models xmlns:xi="http://www.w3.org/2001/XInclude">
+  <model name="CHILD">
+    <input_ports>
+      <port name="I"/>
+    </input_ports>
+    <output_ports>
+      <port name="O"/>
+    </output_ports>
+  </model>
+</models>

diff --git a/tests/net_attr/child/child.pb_type.xml b/tests/net_attr/child/child.pb_type.xml
new file mode 100644
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+++ b/tests/net_attr/child/child.pb_type.xml

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+<?xml version='1.0' encoding='utf-8'?>
+<pb_type xmlns:xi="http://www.w3.org/2001/XInclude" name="CHILD" num_pb="1">
+  <blif_model>.subckt CHILD</blif_model>
+  <input name="I" num_pins="1"/>
+  <output name="O" num_pins="1"/>
+</pb_type>

diff --git a/tests/net_attr/child/child.sim.v b/tests/net_attr/child/child.sim.v
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+++ b/tests/net_attr/child/child.sim.v

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+(* whitebox *)
+module CHILD(
+    input  wire I,
+    output wire O
+);
+
+endmodule

diff --git a/tests/net_attr/golden.model.xml b/tests/net_attr/golden.model.xml
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+++ b/tests/net_attr/golden.model.xml

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+<models xmlns:xi="http://www.w3.org/2001/XInclude">
+  <xi:include href="./child/child.model.xml" xpointer="xpointer(models/child::node())"/>
+</models>

diff --git a/tests/net_attr/golden.pb_type.xml b/tests/net_attr/golden.pb_type.xml
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+++ b/tests/net_attr/golden.pb_type.xml

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+<?xml version='1.0' encoding='utf-8'?>
+<pb_type xmlns:xi="http://www.w3.org/2001/XInclude" name="PARENT" num_pb="1">
+  <input name="I" num_pins="1"/>
+  <output name="O" num_pins="1"/>
+  <pb_type name="child" num_pb="1">
+    <!--old_name CHILD-->
+    <xi:include href="./child/child.pb_type.xml" xpointer="xpointer(pb_type/child::node())"/>
+  </pb_type>
+  <interconnect>
+    <direct>
+      <port name="I" type="input"/>
+      <port from="child" name="I" type="output"/>
+    </direct>
+    <direct>
+      <port from="child" name="O" type="input"/>
+      <port name="O" type="output"/>
+    </direct>
+  </interconnect>
+</pb_type>

diff --git a/tests/net_attr/parent.sim.v b/tests/net_attr/parent.sim.v
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+++ b/tests/net_attr/parent.sim.v

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+`include "./child/child.sim.v"
+
+module PARENT(
+    input  wire I,
+    output wire O
+);
+
+    wire hop1 = I;
+
+    CHILD child (
+    .I(hop1),
+    .O(O)
+    );
+
+endmodule