Addressed PR comments.

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

tests/clocks/input_attr_not_clock/block.sim.v

diff --git a/tests/clocks/input_attr_not_clock/block.sim.v b/tests/clocks/input_attr_not_clock/block.sim.v
index ec59b5c..f87f8b2 100644
--- a/tests/clocks/input_attr_not_clock/block.sim.v
+++ b/tests/clocks/input_attr_not_clock/block.sim.v
@@ -5,13 +5,13 @@
  */
 module BLOCK(a, b, c);
     (* CLOCK=0 *)
-	input wire a;
-	input wire b;
-	output wire c;
-
-	reg r;
-	always @ ( posedge a ) begin
-		r <= b;
-	end
-	assign c = r;
+    input wire a;
+    input wire b;
+    output wire c;
+    
+    reg r;
+    always @ ( posedge a ) begin
+    	r <= b;
+    end
+    assign c = r;
 endmodule

v2x/yosys/utils.py

diff --git a/v2x/yosys/utils.py b/v2x/yosys/utils.py
index 4383161..f6c3597 100644
--- a/v2x/yosys/utils.py
+++ b/v2x/yosys/utils.py
@@ -17,6 +17,25 @@
     """
     Returns true if the port name correspond to a clock according to arbitrary
     regular expressions.
+
+    >>> is_clock_name("data")
+    False
+    >>> is_clock_name("clk")
+    True
+    >>> is_clock_name("Clk")
+    True
+    >>> is_clock_name("Clk_Rst0")
+    False
+    >>> is_clock_name("Data_clk")
+    True
+    >>> is_clock_name("clk99")
+    True
+    >>> is_clock_name("bus_clk99")
+    True
+    >>> is_clock_name("busclk15")
+    True
+    >>> is_clock_name("clkb")
+    True
     """
     match = CLOCK_NAME_REGEX.match(name.lower())
     return match is not None