Sign in
foss-fpga-tools
/
third_party
/
Surelog
/
356a4bf2123fc606ca19fbed9b9c535f149fdec5
/
.
/
SVIncCompil
/
Testcases
/
Icarus
/
ivltests
/
pr708.v
blob: ecd7efb34fbcef35b6a16b110f45869acba01bbf [
file
] [
log
] [
blame
]
module
test
;
parameter PARM
=
1.5
;
reg r
;
initial
begin
case
(
PARM
)
1.0
:
r
<=
'd1;
1.5 : r <= '
d0
;
2.0
:
r
<=
'd1;
default: r <= 1'
bx
;
endcase
#1;
if
(
r
!==
'd0)
$display("FAILED %b != 0", r);
else
$display("PASSED");
end
endmodule