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foss-fpga-tools
/
third_party
/
Surelog
/
356a4bf2123fc606ca19fbed9b9c535f149fdec5
/
.
/
SVIncCompil
/
Testcases
/
UtdSV
/
simple_task.v
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module
simple_task
();
task convert
;
input
[
7
:
0
]
temp_in
;
output
[
7
:
0
]
temp_out
;
begin
temp_out
=
(
9
/
5
)
*(
temp_in
+
32
);
end
endtask
endmodule
