blob: 360fb330f5186b4b2104eebf2132424008028e7e [file] [log] [blame]
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2017 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
always_comb @(*) begin
$stop;
end
endmodule