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foss-fpga-tools
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third_party
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Surelog
/
356a4bf2123fc606ca19fbed9b9c535f149fdec5
/
.
/
SVIncCompil
/
Testcases
/
YosysBigSim
/
bch_verilog
/
sim
/
settings.sh
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YOSYS_GLOBRST
=
true
RTL
=
"bch_decode.v bch_encode.v bch_math.v bch_syndrome_method1.v
bch_syndrome_method2.v bch_syndrome.v chien.v dec_decode.v
tmec_decode_parallel.v tmec_decode_serial.v tmec_decode.v"
SIM
=
"tb_sim.v sim.v"
