| ******************************************** |
| * SURELOG System Verilog Compiler/Linter * |
| ******************************************** |
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| [INFO :CM0023] Creating log file ./slpp_unit/surelog.log. |
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| [INFO :CM0024] Executing with 4 threads. |
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| [INFO :CM0020] Separate compilation-unit mode is on. |
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| [WARNI:PA0205] rtl/softusb_navre.v:18 No timescale set for "softusb_navre". |
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| [WARNI:PA0205] sim/bench.v:2 No timescale set for "testbench". |
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| [INFO :CP0300] Compilation... |
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| [INFO :CP0303] rtl/softusb_navre.v:18 Compile module "work@softusb_navre". |
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| [INFO :CP0303] sim/bench.v:2 Compile module "work@testbench". |
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| [NOTE :CP0309] rtl/softusb_navre.v:26 Implicit port type (wire) for "pmem_a", |
| there are 2 more instances of this message. |
| |
| [INFO :EL0526] Design Elaboration... |
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| [NOTE :EL0503] sim/bench.v:2 Top level module "work@testbench". |
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| [NOTE :EL0508] Nb Top level modules: 1. |
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| [NOTE :EL0509] Max instance depth: 2. |
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| [NOTE :EL0510] Nb instances: 2. |
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| [NOTE :EL0511] Nb leaf instances: 0. |
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| [ FATAL] : 0 |
| [ ERROR] : 0 |
| [WARNING] : 2 |
| [ NOTE] : 6 |
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| ******************************************** |
| * End SURELOG SVerilog Compiler/Linter * |
| ******************************************** |
| |
| 2.66user 0.03system 0:02.85elapsed 94%CPU (0avgtext+0avgdata 92876maxresident)k |
| 64inputs+72outputs (0major+20617minor)pagefaults 0swaps |
