blob: c924c69c90a43a9cda48bab320a70619ab2cdc6e [file] [log] [blame]
read_verilog softusb_navre/rtl/softusb_navre.v
design -copy-to equiv -as gold softusb_navre
synth -encfile softusb_navre/gen/equiv.enc
design -copy-to equiv -as gate softusb_navre
design -load equiv
proc; memory
equiv_make -encfile softusb_navre/gen/equiv.enc gold gate equiv
hierarchy -top equiv
opt -keepdc
equiv_simple -undef
equiv_induct
equiv_status -assert