| Formality (R) | |
| Version C-2009.06-SP3 -- Oct 19, 2009 | |
| Copyright (c) 1988-2013 by Synopsys, Inc. | |
| ALL RIGHTS RESERVED | |
| This program is proprietary and confidential information of Synopsys, Inc. | |
| and may be used and disclosed only as authorized in a license agreement | |
| controlling such use and disclosure. | |
| ** Highlights of Formality 2009.06 ** | |
| - DC Ultra 2009.06 optimization support | |
| - Debugging guidance for failing and aborted points (new command: analyze_points) | |
| - Power domain color highlighting for logic cone and schematic views | |
| * Please refer to the Formality Release Notes for details and additional enhancements | |
| Hostname: morpheus5 (amd64) | |
| Current time: Fri May 17 15:07:50 2013 | |
| Loading db file '/opt/eda/iac/tools/fm/2009_06/libraries/syn/gtech.db' | |
| set hdlin_ignore_full_case false | |
| false | |
| set hdlin_warn_on_mismatch_message "FMR_ELAB-115 FMR_ELAB-146 FMR_ELAB-147" | |
| FMR_ELAB-115 FMR_ELAB-146 FMR_ELAB-147 | |
| read_verilog -container r -libname WORK -01 { rtl/pcm_slv_top.v } | |
| Loading verilog file '/home/lva/vhdl/vhdl1/yosys-tests/ss_pcm/rtl/pcm_slv_top.v' | |
| Loading include file '/home/lva/vhdl/vhdl1/yosys-tests/ss_pcm/rtl/timescale.v' | |
| Current container set to 'r' | |
| 1 | |
| set_top r:/WORK/pcm_slv_top | |
| Setting top design to 'r:/WORK/pcm_slv_top' | |
| Status: Elaborating design pcm_slv_top ... | |
| Status: Implementing inferred operators... | |
| Top design successfully set to 'r:/WORK/pcm_slv_top' | |
| Reference design set to 'r:/WORK/pcm_slv_top' | |
| 1 | |
| read_verilog -container i -libname WORK -01 output/synth.v | |
| Loading verilog file '/home/lva/vhdl/vhdl1/yosys-tests/ss_pcm/output/synth.v' | |
| Current container set to 'i' | |
| 1 | |
| set_top i:/WORK/pcm_slv_top | |
| Setting top design to 'i:/WORK/pcm_slv_top' | |
| Status: Elaborating design pcm_slv_top ... | |
| Status: Implementing inferred operators... | |
| Top design successfully set to 'i:/WORK/pcm_slv_top' | |
| Implementation design set to 'i:/WORK/pcm_slv_top' | |
| 1 | |
| verify | |
| Reference design is 'r:/WORK/pcm_slv_top' | |
| Implementation design is 'i:/WORK/pcm_slv_top' | |
| Status: Checking designs... | |
| Status: Building verification models... | |
| Status: Generating datapath components ... | |
| Status: Qualifying datapath components ... | |
| Status: Datapath qualification complete. | |
| Status: Matching... | |
| *********************************** Matching Results *********************************** | |
| 80 Compare points matched by name | |
| 16 Compare points matched by signature analysis | |
| 0 Compare points matched by topology | |
| 19 Matched primary inputs, black-box outputs | |
| 0(0) Unmatched reference(implementation) compare points | |
| 0(0) Unmatched reference(implementation) primary inputs, black-box outputs | |
| 5(0) Unmatched reference(implementation) unread points | |
| **************************************************************************************** | |
| Info: Formality Guide Files (SVF) can improve matching performance and success by automating setup. | |
| Status: Verifying... | |
| ********************************* Verification Results ********************************* | |
| Verification SUCCEEDED | |
| ---------------------- | |
| Reference design: r:/WORK/pcm_slv_top | |
| Implementation design: i:/WORK/pcm_slv_top | |
| 96 Passing compare points | |
| ---------------------------------------------------------------------------------------- | |
| Matched Compare Points BBPin Loop BBNet Cut Port DFF LAT TOTAL | |
| ---------------------------------------------------------------------------------------- | |
| Passing (equivalent) 0 0 0 0 9 87 0 96 | |
| Failing (not equivalent) 0 0 0 0 0 0 0 0 | |
| **************************************************************************************** | |
| 1 | |
| exit | |
| Maximum memory usage for this session: 21184 KB | |
| CPU usage for this session: 0.63 seconds | |
| Thank you for using Formality (R)! |