SVIncCompil/Testcases/YosysOldTests/usb_phy/cache/synth.log - third_party/Surelog - Git at Google



             /-----------------------------------------------------------------------------\

            
             |                                                                             |

            
             |  yosys -- Yosys Open SYnthesis Suite                                        |

            
             |                                                                             |

            
             |  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>                   |

            
             |                                                                             |

            
             |  Permission to use, copy, modify, and/or distribute this software for any   |

            
             |  purpose with or without fee is hereby granted, provided that the above     |

            
             |  copyright notice and this permission notice appear in all copies.          |

            
             |                                                                             |

            
             |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES   |

            
             |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF           |

            
             |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR    |

            
             |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES     |

            
             |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN      |

            
             |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF    |

            
             |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.             |

            
             |                                                                             |

            
             \-----------------------------------------------------------------------------/


            -- Executing script file `scripts/synth.ys' --


            1. Executing Verilog-2005 frontend.

            
            Full command line: read_verilog rtl/usb_phy.v

            
            Parsing Verilog input from `rtl/usb_phy.v' to AST representation.

            
            Generating RTLIL representation for module `\usb_phy'.

            
            Successfully finished Verilog frontend.


            2. Executing Verilog-2005 frontend.

            
            Full command line: read_verilog rtl/usb_rx_phy.v

            
            Parsing Verilog input from `rtl/usb_rx_phy.v' to AST representation.

            
            Warning: Found one of those horrible `synopsys full_case' comments.

            
            It is strongly suggested to use verilog x-values and default branches instead!

            
            Warning: Found one of those horrible `synopsys parallel_case' comments.

            
            It is strongly suggested to use verilog `parallel_case' attributes instead!

            
            Warning: Found one of those horrible `synopsys full_case' comments.

            
            It is strongly suggested to use verilog x-values and default branches instead!

            
            Warning: Found one of those horrible `synopsys parallel_case' comments.

            
            It is strongly suggested to use verilog `parallel_case' attributes instead!

            
            Generating RTLIL representation for module `\usb_rx_phy'.

            
            Note: Assuming pure combinatorial block at rtl/usb_rx_phy.v:211 in

            
            compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending

            
            use of @* instead of @(...) for better match of synthesis and simulation.

            
            Note: Assuming pure combinatorial block at rtl/usb_rx_phy.v:263 in

            
            compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending

            
            use of @* instead of @(...) for better match of synthesis and simulation.

            
            Successfully finished Verilog frontend.


            3. Executing Verilog-2005 frontend.

            
            Full command line: read_verilog rtl/usb_tx_phy.v

            
            Parsing Verilog input from `rtl/usb_tx_phy.v' to AST representation.

            
            Warning: Found one of those horrible `synopsys full_case' comments.

            
            It is strongly suggested to use verilog x-values and default branches instead!

            
            Warning: Found one of those horrible `synopsys parallel_case' comments.

            
            It is strongly suggested to use verilog `parallel_case' attributes instead!

            
            Warning: Found one of those horrible `synopsys full_case' comments.

            
            It is strongly suggested to use verilog x-values and default branches instead!

            
            Warning: Found one of those horrible `synopsys parallel_case' comments.

            
            It is strongly suggested to use verilog `parallel_case' attributes instead!

            
            Generating RTLIL representation for module `\usb_tx_phy'.

            
            Note: Assuming pure combinatorial block at rtl/usb_tx_phy.v:418 in

            
            compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending

            
            use of @* instead of @(...) for better match of synthesis and simulation.

            
            Successfully finished Verilog frontend.


            4. Executing HIERARCHY pass (managing design hierarchy).

            
            Full command line: hierarchy -top usb_phy

            
            Top module: \usb_phy

            
            Used module: \usb_rx_phy

            
            Used module: \usb_tx_phy

            
            Removed 0 unused modules.

            
            Top module: \usb_phy

            
            Used module: \usb_rx_phy

            
            Used module: \usb_tx_phy

            
            Removed 0 unused modules.


            -- Executing script file `../scripts/generic.ys' --


            5. Executing HIERARCHY pass (managing design hierarchy).


            6. Executing PROC pass (convert processes to netlists).


            6.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).

            
            Cleaned up 0 empty switches.


            6.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).

            
            Removed a total of 0 dead cases.


            6.3. Executing PROC_ARST pass (detect async resets in processes).


            6.4. Executing PROC_MUX pass (convert decision trees to multiplexers).

            
            Creating decoders for process `\usb_phy.$proc$rtl/usb_phy.v:172$1'.

            
              creating decoder for signal `$0\rst_cnt[4:0]'.

            
            Creating decoders for process `\usb_phy.$proc$rtl/usb_phy.v:180$7'.

            
              creating decoder for signal `$0\usb_rst[0:0]'.

            
            Creating decoders for process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:144$11'.

            
              creating decoder for signal `$0\rx_en[0:0]'.

            
            Creating decoders for process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:145$12'.

            
              creating decoder for signal `$0\sync_err[0:0]'.

            
            Creating decoders for process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:157$15'.

            
              creating decoder for signal `$0\rxd_s0[0:0]'.

            
            Creating decoders for process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:158$16'.

            
              creating decoder for signal `$0\rxd_s1[0:0]'.

            
            Creating decoders for process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:159$17'.

            
              creating decoder for signal `$0\rxd_s[0:0]'.

            
            Creating decoders for process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:164$22'.

            
              creating decoder for signal `$0\rxdp_s0[0:0]'.

            
            Creating decoders for process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:165$23'.

            
              creating decoder for signal `$0\rxdp_s1[0:0]'.

            
            Creating decoders for process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:166$24'.

            
              creating decoder for signal `$0\rxdp_s_r[0:0]'.

            
            Creating decoders for process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:167$26'.

            
              creating decoder for signal `$0\rxdp_s[0:0]'.

            
            Creating decoders for process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:169$29'.

            
              creating decoder for signal `$0\rxdn_s0[0:0]'.

            
            Creating decoders for process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:170$30'.

            
              creating decoder for signal `$0\rxdn_s1[0:0]'.

            
            Creating decoders for process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:171$31'.

            
              creating decoder for signal `$0\rxdn_s_r[0:0]'.

            
            Creating decoders for process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:172$33'.

            
              creating decoder for signal `$0\rxdn_s[0:0]'.

            
            Creating decoders for process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:178$43'.

            
              creating decoder for signal `$0\se0_s[0:0]'.

            
            Creating decoders for process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:197$44'.

            
              creating decoder for signal `$0\rxd_r[0:0]'.

            
            Creating decoders for process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:206$46'.

            
              creating decoder for signal `$0\dpll_state[1:0]'.

            
            Creating decoders for process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:211$48'.

            
              creating decoder for signal `$0\dpll_next_state[1:0]'.

            
              creating decoder for signal `$0\fs_ce_d[0:0]'.

            
              creating decoder for signal `$1\fs_ce_d[0:0]'.

            
              creating decoder for signal `$1\dpll_next_state[1:0]'.

            
              creating decoder for signal `$2\dpll_next_state[1:0]'.

            
              creating decoder for signal `$3\dpll_next_state[1:0]'.

            
              creating decoder for signal `$4\dpll_next_state[1:0]'.

            
              creating decoder for signal `$5\dpll_next_state[1:0]'.

            
            Creating decoders for process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:236$53'.

            
              creating decoder for signal `$0\fs_ce_r1[0:0]'.

            
            Creating decoders for process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:237$54'.

            
              creating decoder for signal `$0\fs_ce_r2[0:0]'.

            
            Creating decoders for process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:238$55'.

            
              creating decoder for signal `$0\fs_ce[0:0]'.

            
            Creating decoders for process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:258$56'.

            
              creating decoder for signal `$0\fs_state[2:0]'.

            
            Creating decoders for process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:263$58'.

            
              creating decoder for signal `$0\fs_next_state[2:0]'.

            
              creating decoder for signal `$0\sync_err_d[0:0]'.

            
              creating decoder for signal `$0\synced_d[0:0]'.

            
              creating decoder for signal `$1\fs_next_state[2:0]'.

            
              creating decoder for signal `$1\sync_err_d[0:0]'.

            
              creating decoder for signal `$1\synced_d[0:0]'.

            
              creating decoder for signal `$2\sync_err_d[0:0]'.

            
              creating decoder for signal `$2\synced_d[0:0]'.

            
              creating decoder for signal `$2\fs_next_state[2:0]'.

            
              creating decoder for signal `$3\fs_next_state[2:0]'.

            
              creating decoder for signal `$3\sync_err_d[0:0]'.

            
              creating decoder for signal `$4\fs_next_state[2:0]'.

            
              creating decoder for signal `$4\sync_err_d[0:0]'.

            
              creating decoder for signal `$5\fs_next_state[2:0]'.

            
              creating decoder for signal `$5\sync_err_d[0:0]'.

            
              creating decoder for signal `$6\fs_next_state[2:0]'.

            
              creating decoder for signal `$6\sync_err_d[0:0]'.

            
              creating decoder for signal `$7\fs_next_state[2:0]'.

            
              creating decoder for signal `$7\sync_err_d[0:0]'.

            
              creating decoder for signal `$3\synced_d[0:0]'.

            
              creating decoder for signal `$8\fs_next_state[2:0]'.

            
              creating decoder for signal `$8\sync_err_d[0:0]'.

            
              creating decoder for signal `$9\fs_next_state[2:0]'.

            
              creating decoder for signal `$4\synced_d[0:0]'.

            
              creating decoder for signal `$9\sync_err_d[0:0]'.

            
              creating decoder for signal `$10\fs_next_state[2:0]'.

            
              creating decoder for signal `$5\synced_d[0:0]'.

            
            Creating decoders for process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:350$73'.

            
              creating decoder for signal `$0\rx_active[0:0]'.

            
            Creating decoders for process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:358$77'.

            
              creating decoder for signal `$0\rx_valid_r[0:0]'.

            
            Creating decoders for process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:368$78'.

            
              creating decoder for signal `$0\sd_r[0:0]'.

            
            Creating decoders for process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:374$79'.

            
              creating decoder for signal `$0\sd_nrzi[0:0]'.

            
            Creating decoders for process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:390$85'.

            
              creating decoder for signal `$0\one_cnt[2:0]'.

            
            Creating decoders for process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:404$92'.

            
              creating decoder for signal `$0\bit_stuff_err[0:0]'.

            
            Creating decoders for process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:411$98'.

            
              creating decoder for signal `$0\shift_en[0:0]'.

            
            Creating decoders for process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:414$100'.

            
              creating decoder for signal `$0\hold_reg[7:0]'.

            
            Creating decoders for process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:426$104'.

            
              creating decoder for signal `$0\bit_cnt[2:0]'.

            
            Creating decoders for process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:437$110'.

            
              creating decoder for signal `$0\rx_valid1[0:0]'.

            
            Creating decoders for process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:445$119'.

            
              creating decoder for signal `$0\rx_valid[0:0]'.

            
            Creating decoders for process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:447$123'.

            
              creating decoder for signal `$0\se0_r[0:0]'.

            
            Creating decoders for process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:449$124'.

            
              creating decoder for signal `$0\byte_err[0:0]'.

            
            Creating decoders for process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:149$130'.

            
              creating decoder for signal `$0\TxReady_o[0:0]'.

            
            Creating decoders for process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:154$133'.

            
              creating decoder for signal `$0\ld_data[0:0]'.

            
            Creating decoders for process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:164$134'.

            
              creating decoder for signal `$0\tx_ip[0:0]'.

            
            Creating decoders for process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:175$136'.

            
              creating decoder for signal `$0\tx_ip_sync[0:0]'.

            
            Creating decoders for process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:188$138'.

            
              creating decoder for signal `$0\data_done[0:0]'.

            
            Creating decoders for process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:204$143'.

            
              creating decoder for signal `$0\bit_cnt[2:0]'.

            
            Creating decoders for process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:214$149'.

            
              creating decoder for signal `$0\sd_raw_o[0:0]'.

            
            Creating decoders for process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:228$151'.

            
              creating decoder for signal `$0\sft_done[0:0]'.

            
            Creating decoders for process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:231$155'.

            
              creating decoder for signal `$0\sft_done_r[0:0]'.

            
            Creating decoders for process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:237$158'.

            
              creating decoder for signal `$0\hold_reg[7:0]'.

            
            Creating decoders for process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:242$159'.

            
              creating decoder for signal `$0\hold_reg_d[7:0]'.

            
            Creating decoders for process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:252$160'.

            
              creating decoder for signal `$0\one_cnt[2:0]'.

            
            Creating decoders for process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:269$167'.

            
              creating decoder for signal `$0\sd_bs_o[0:0]'.

            
            Creating decoders for process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:283$172'.

            
              creating decoder for signal `$0\sd_nrzi_o[0:0]'.

            
            Creating decoders for process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:299$179'.

            
              creating decoder for signal `$0\append_eop[0:0]'.

            
            Creating decoders for process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:310$181'.

            
              creating decoder for signal `$0\append_eop_sync1[0:0]'.

            
            Creating decoders for process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:319$183'.

            
              creating decoder for signal `$0\append_eop_sync2[0:0]'.

            
            Creating decoders for process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:328$185'.

            
              creating decoder for signal `$0\append_eop_sync3[0:0]'.

            
            Creating decoders for process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:338$190'.

            
              creating decoder for signal `$0\append_eop_sync4[0:0]'.

            
            Creating decoders for process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:354$192'.

            
              creating decoder for signal `$0\txoe_r1[0:0]'.

            
            Creating decoders for process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:363$194'.

            
              creating decoder for signal `$0\txoe_r2[0:0]'.

            
            Creating decoders for process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:372$196'.

            
              creating decoder for signal `$0\txoe[0:0]'.

            
            Creating decoders for process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:386$200'.

            
              creating decoder for signal `$0\txdp[0:0]'.

            
            Creating decoders for process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:397$205'.

            
              creating decoder for signal `$0\txdn[0:0]'.

            
            Creating decoders for process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:413$211'.

            
              creating decoder for signal `$0\state[2:0]'.

            
            Creating decoders for process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:418$213'.

            
              creating decoder for signal `$0\ld_data_d[0:0]'.

            
              creating decoder for signal `$0\ld_eop_d[0:0]'.

            
              creating decoder for signal `$0\ld_sop_d[0:0]'.

            
              creating decoder for signal `$0\next_state[2:0]'.

            
              creating decoder for signal `$0\tx_ready_d[0:0]'.

            
              creating decoder for signal `$1\ld_data_d[0:0]'.

            
              creating decoder for signal `$1\ld_eop_d[0:0]'.

            
              creating decoder for signal `$1\tx_ready_d[0:0]'.

            
              creating decoder for signal `$1\ld_sop_d[0:0]'.

            
              creating decoder for signal `$1\next_state[2:0]'.

            
              creating decoder for signal `$2\ld_sop_d[0:0]'.

            
              creating decoder for signal `$2\next_state[2:0]'.

            
              creating decoder for signal `$2\tx_ready_d[0:0]'.

            
              creating decoder for signal `$2\ld_data_d[0:0]'.

            
              creating decoder for signal `$3\next_state[2:0]'.

            
              creating decoder for signal `$2\ld_eop_d[0:0]'.

            
              creating decoder for signal `$4\next_state[2:0]'.

            
              creating decoder for signal `$3\tx_ready_d[0:0]'.

            
              creating decoder for signal `$3\ld_data_d[0:0]'.

            
              creating decoder for signal `$5\next_state[2:0]'.

            
              creating decoder for signal `$6\next_state[2:0]'.

            
              creating decoder for signal `$7\next_state[2:0]'.


            6.5. Executing PROC_DFF pass (convert process syncs to FFs).

            
            Creating register for signal `\usb_phy.\rst_cnt' using process `\usb_phy.$proc$rtl/usb_phy.v:172$1'.

            
              created $dff cell `$procdff$1980' with positive edge clock.

            
            Creating register for signal `\usb_phy.\usb_rst' using process `\usb_phy.$proc$rtl/usb_phy.v:180$7'.

            
              created $dff cell `$procdff$1981' with positive edge clock.

            
            Creating register for signal `\usb_rx_phy.\rx_en' using process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:144$11'.

            
              created $dff cell `$procdff$1982' with positive edge clock.

            
            Creating register for signal `\usb_rx_phy.\sync_err' using process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:145$12'.

            
              created $dff cell `$procdff$1983' with positive edge clock.

            
            Creating register for signal `\usb_rx_phy.\rxd_s0' using process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:157$15'.

            
              created $dff cell `$procdff$1984' with positive edge clock.

            
            Creating register for signal `\usb_rx_phy.\rxd_s1' using process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:158$16'.

            
              created $dff cell `$procdff$1985' with positive edge clock.

            
            Creating register for signal `\usb_rx_phy.\rxd_s' using process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:159$17'.

            
              created $dff cell `$procdff$1986' with positive edge clock.

            
            Creating register for signal `\usb_rx_phy.\rxdp_s0' using process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:164$22'.

            
              created $dff cell `$procdff$1987' with positive edge clock.

            
            Creating register for signal `\usb_rx_phy.\rxdp_s1' using process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:165$23'.

            
              created $dff cell `$procdff$1988' with positive edge clock.

            
            Creating register for signal `\usb_rx_phy.\rxdp_s_r' using process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:166$24'.

            
              created $dff cell `$procdff$1989' with positive edge clock.

            
            Creating register for signal `\usb_rx_phy.\rxdp_s' using process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:167$26'.

            
              created $dff cell `$procdff$1990' with positive edge clock.

            
            Creating register for signal `\usb_rx_phy.\rxdn_s0' using process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:169$29'.

            
              created $dff cell `$procdff$1991' with positive edge clock.

            
            Creating register for signal `\usb_rx_phy.\rxdn_s1' using process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:170$30'.

            
              created $dff cell `$procdff$1992' with positive edge clock.

            
            Creating register for signal `\usb_rx_phy.\rxdn_s_r' using process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:171$31'.

            
              created $dff cell `$procdff$1993' with positive edge clock.

            
            Creating register for signal `\usb_rx_phy.\rxdn_s' using process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:172$33'.

            
              created $dff cell `$procdff$1994' with positive edge clock.

            
            Creating register for signal `\usb_rx_phy.\se0_s' using process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:178$43'.

            
              created $dff cell `$procdff$1995' with positive edge clock.

            
            Creating register for signal `\usb_rx_phy.\rxd_r' using process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:197$44'.

            
              created $dff cell `$procdff$1996' with positive edge clock.

            
            Creating register for signal `\usb_rx_phy.\dpll_state' using process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:206$46'.

            
              created $dff cell `$procdff$1997' with positive edge clock.

            
            Creating register for signal `\usb_rx_phy.\dpll_next_state' using process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:211$48'.

            
              created direct connection (no actual register cell created).

            
            Creating register for signal `\usb_rx_phy.\fs_ce_d' using process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:211$48'.

            
              created direct connection (no actual register cell created).

            
            Creating register for signal `\usb_rx_phy.\fs_ce_r1' using process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:236$53'.

            
              created $dff cell `$procdff$1998' with positive edge clock.

            
            Creating register for signal `\usb_rx_phy.\fs_ce_r2' using process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:237$54'.

            
              created $dff cell `$procdff$1999' with positive edge clock.

            
            Creating register for signal `\usb_rx_phy.\fs_ce' using process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:238$55'.

            
              created $dff cell `$procdff$2000' with positive edge clock.

            
            Creating register for signal `\usb_rx_phy.\fs_state' using process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:258$56'.

            
              created $dff cell `$procdff$2001' with positive edge clock.

            
            Creating register for signal `\usb_rx_phy.\fs_next_state' using process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:263$58'.

            
              created direct connection (no actual register cell created).

            
            Creating register for signal `\usb_rx_phy.\sync_err_d' using process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:263$58'.

            
              created direct connection (no actual register cell created).

            
            Creating register for signal `\usb_rx_phy.\synced_d' using process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:263$58'.

            
              created direct connection (no actual register cell created).

            
            Creating register for signal `\usb_rx_phy.\rx_active' using process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:350$73'.

            
              created $dff cell `$procdff$2002' with positive edge clock.

            
            Creating register for signal `\usb_rx_phy.\rx_valid_r' using process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:358$77'.

            
              created $dff cell `$procdff$2003' with positive edge clock.

            
            Creating register for signal `\usb_rx_phy.\sd_r' using process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:368$78'.

            
              created $dff cell `$procdff$2004' with positive edge clock.

            
            Creating register for signal `\usb_rx_phy.\sd_nrzi' using process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:374$79'.

            
              created $dff cell `$procdff$2005' with positive edge clock.

            
            Creating register for signal `\usb_rx_phy.\one_cnt' using process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:390$85'.

            
              created $dff cell `$procdff$2006' with positive edge clock.

            
            Creating register for signal `\usb_rx_phy.\bit_stuff_err' using process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:404$92'.

            
              created $dff cell `$procdff$2007' with positive edge clock.

            
            Creating register for signal `\usb_rx_phy.\shift_en' using process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:411$98'.

            
              created $dff cell `$procdff$2008' with positive edge clock.

            
            Creating register for signal `\usb_rx_phy.\hold_reg' using process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:414$100'.

            
              created $dff cell `$procdff$2009' with positive edge clock.

            
            Creating register for signal `\usb_rx_phy.\bit_cnt' using process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:426$104'.

            
              created $dff cell `$procdff$2010' with positive edge clock.

            
            Creating register for signal `\usb_rx_phy.\rx_valid1' using process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:437$110'.

            
              created $dff cell `$procdff$2011' with positive edge clock.

            
            Creating register for signal `\usb_rx_phy.\rx_valid' using process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:445$119'.

            
              created $dff cell `$procdff$2012' with positive edge clock.

            
            Creating register for signal `\usb_rx_phy.\se0_r' using process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:447$123'.

            
              created $dff cell `$procdff$2013' with positive edge clock.

            
            Creating register for signal `\usb_rx_phy.\byte_err' using process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:449$124'.

            
              created $dff cell `$procdff$2014' with positive edge clock.

            
            Creating register for signal `\usb_tx_phy.\TxReady_o' using process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:149$130'.

            
              created $dff cell `$procdff$2015' with positive edge clock.

            
            Creating register for signal `\usb_tx_phy.\ld_data' using process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:154$133'.

            
              created $dff cell `$procdff$2016' with positive edge clock.

            
            Creating register for signal `\usb_tx_phy.\tx_ip' using process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:164$134'.

            
              created $dff cell `$procdff$2017' with positive edge clock.

            
            Creating register for signal `\usb_tx_phy.\tx_ip_sync' using process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:175$136'.

            
              created $dff cell `$procdff$2018' with positive edge clock.

            
            Creating register for signal `\usb_tx_phy.\data_done' using process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:188$138'.

            
              created $dff cell `$procdff$2019' with positive edge clock.

            
            Creating register for signal `\usb_tx_phy.\bit_cnt' using process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:204$143'.

            
              created $dff cell `$procdff$2020' with positive edge clock.

            
            Creating register for signal `\usb_tx_phy.\sd_raw_o' using process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:214$149'.

            
              created $dff cell `$procdff$2021' with positive edge clock.

            
            Creating register for signal `\usb_tx_phy.\sft_done' using process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:228$151'.

            
              created $dff cell `$procdff$2022' with positive edge clock.

            
            Creating register for signal `\usb_tx_phy.\sft_done_r' using process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:231$155'.

            
              created $dff cell `$procdff$2023' with positive edge clock.

            
            Creating register for signal `\usb_tx_phy.\hold_reg' using process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:237$158'.

            
              created $dff cell `$procdff$2024' with positive edge clock.

            
            Creating register for signal `\usb_tx_phy.\hold_reg_d' using process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:242$159'.

            
              created $dff cell `$procdff$2025' with positive edge clock.

            
            Creating register for signal `\usb_tx_phy.\one_cnt' using process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:252$160'.

            
              created $dff cell `$procdff$2026' with positive edge clock.

            
            Creating register for signal `\usb_tx_phy.\sd_bs_o' using process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:269$167'.

            
              created $dff cell `$procdff$2027' with positive edge clock.

            
            Creating register for signal `\usb_tx_phy.\sd_nrzi_o' using process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:283$172'.

            
              created $dff cell `$procdff$2028' with positive edge clock.

            
            Creating register for signal `\usb_tx_phy.\append_eop' using process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:299$179'.

            
              created $dff cell `$procdff$2029' with positive edge clock.

            
            Creating register for signal `\usb_tx_phy.\append_eop_sync1' using process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:310$181'.

            
              created $dff cell `$procdff$2030' with positive edge clock.

            
            Creating register for signal `\usb_tx_phy.\append_eop_sync2' using process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:319$183'.

            
              created $dff cell `$procdff$2031' with positive edge clock.

            
            Creating register for signal `\usb_tx_phy.\append_eop_sync3' using process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:328$185'.

            
              created $dff cell `$procdff$2032' with positive edge clock.

            
            Creating register for signal `\usb_tx_phy.\append_eop_sync4' using process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:338$190'.

            
              created $dff cell `$procdff$2033' with positive edge clock.

            
            Creating register for signal `\usb_tx_phy.\txoe_r1' using process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:354$192'.

            
              created $dff cell `$procdff$2034' with positive edge clock.

            
            Creating register for signal `\usb_tx_phy.\txoe_r2' using process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:363$194'.

            
              created $dff cell `$procdff$2035' with positive edge clock.

            
            Creating register for signal `\usb_tx_phy.\txoe' using process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:372$196'.

            
              created $dff cell `$procdff$2036' with positive edge clock.

            
            Creating register for signal `\usb_tx_phy.\txdp' using process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:386$200'.

            
              created $dff cell `$procdff$2037' with positive edge clock.

            
            Creating register for signal `\usb_tx_phy.\txdn' using process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:397$205'.

            
              created $dff cell `$procdff$2038' with positive edge clock.

            
            Creating register for signal `\usb_tx_phy.\state' using process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:413$211'.

            
              created $dff cell `$procdff$2039' with positive edge clock.

            
            Creating register for signal `\usb_tx_phy.\ld_data_d' using process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:418$213'.

            
              created direct connection (no actual register cell created).

            
            Creating register for signal `\usb_tx_phy.\ld_eop_d' using process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:418$213'.

            
              created direct connection (no actual register cell created).

            
            Creating register for signal `\usb_tx_phy.\ld_sop_d' using process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:418$213'.

            
              created direct connection (no actual register cell created).

            
            Creating register for signal `\usb_tx_phy.\next_state' using process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:418$213'.

            
              created direct connection (no actual register cell created).

            
            Creating register for signal `\usb_tx_phy.\tx_ready_d' using process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:418$213'.

            
              created direct connection (no actual register cell created).


            6.6. Executing PROC_CLEAN pass (remove empty switches from decision trees).

            
            Found and cleaned up 3 empty switches in `\usb_phy.$proc$rtl/usb_phy.v:172$1'.

            
            Removing empty process `\usb_phy.$proc$rtl/usb_phy.v:172$1'.

            
            Removing empty process `\usb_phy.$proc$rtl/usb_phy.v:180$7'.

            
            Removing empty process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:144$11'.

            
            Removing empty process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:145$12'.

            
            Removing empty process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:157$15'.

            
            Removing empty process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:158$16'.

            
            Found and cleaned up 2 empty switches in `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:159$17'.

            
            Removing empty process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:159$17'.

            
            Removing empty process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:164$22'.

            
            Removing empty process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:165$23'.

            
            Removing empty process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:166$24'.

            
            Removing empty process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:167$26'.

            
            Removing empty process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:169$29'.

            
            Removing empty process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:170$30'.

            
            Removing empty process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:171$31'.

            
            Removing empty process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:172$33'.

            
            Found and cleaned up 1 empty switch in `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:178$43'.

            
            Removing empty process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:178$43'.

            
            Removing empty process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:197$44'.

            
            Found and cleaned up 1 empty switch in `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:206$46'.

            
            Removing empty process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:206$46'.

            
            Found and cleaned up 5 empty switches in `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:211$48'.

            
            Removing empty process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:211$48'.

            
            Removing empty process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:236$53'.

            
            Removing empty process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:237$54'.

            
            Removing empty process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:238$55'.

            
            Found and cleaned up 1 empty switch in `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:258$56'.

            
            Removing empty process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:258$56'.

            
            Found and cleaned up 11 empty switches in `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:263$58'.

            
            Removing empty process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:263$58'.

            
            Found and cleaned up 3 empty switches in `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:350$73'.

            
            Removing empty process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:350$73'.

            
            Found and cleaned up 2 empty switches in `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:358$77'.

            
            Removing empty process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:358$77'.

            
            Found and cleaned up 1 empty switch in `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:368$78'.

            
            Removing empty process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:368$78'.

            
            Found and cleaned up 3 empty switches in `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:374$79'.

            
            Removing empty process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:374$79'.

            
            Found and cleaned up 4 empty switches in `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:390$85'.

            
            Removing empty process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:390$85'.

            
            Removing empty process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:404$92'.

            
            Found and cleaned up 1 empty switch in `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:411$98'.

            
            Removing empty process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:411$98'.

            
            Found and cleaned up 1 empty switch in `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:414$100'.

            
            Removing empty process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:414$100'.

            
            Found and cleaned up 3 empty switches in `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:426$104'.

            
            Removing empty process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:426$104'.

            
            Found and cleaned up 3 empty switches in `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:437$110'.

            
            Removing empty process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:437$110'.

            
            Removing empty process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:445$119'.

            
            Removing empty process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:447$123'.

            
            Removing empty process `\usb_rx_phy.$proc$rtl/usb_rx_phy.v:449$124'.

            
            Found and cleaned up 1 empty switch in `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:149$130'.

            
            Removing empty process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:149$130'.

            
            Removing empty process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:154$133'.

            
            Found and cleaned up 3 empty switches in `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:164$134'.

            
            Removing empty process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:164$134'.

            
            Found and cleaned up 2 empty switches in `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:175$136'.

            
            Removing empty process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:175$136'.

            
            Found and cleaned up 3 empty switches in `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:188$138'.

            
            Removing empty process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:188$138'.

            
            Found and cleaned up 3 empty switches in `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:204$143'.

            
            Removing empty process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:204$143'.

            
            Found and cleaned up 2 empty switches in `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:214$149'.

            
            Removing empty process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:214$149'.

            
            Removing empty process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:228$151'.

            
            Removing empty process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:231$155'.

            
            Found and cleaned up 2 empty switches in `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:237$158'.

            
            Removing empty process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:237$158'.

            
            Removing empty process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:242$159'.

            
            Found and cleaned up 4 empty switches in `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:252$160'.

            
            Removing empty process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:252$160'.

            
            Found and cleaned up 2 empty switches in `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:269$167'.

            
            Removing empty process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:269$167'.

            
            Found and cleaned up 3 empty switches in `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:283$172'.

            
            Removing empty process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:283$172'.

            
            Found and cleaned up 3 empty switches in `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:299$179'.

            
            Removing empty process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:299$179'.

            
            Found and cleaned up 2 empty switches in `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:310$181'.

            
            Removing empty process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:310$181'.

            
            Found and cleaned up 2 empty switches in `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:319$183'.

            
            Removing empty process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:319$183'.

            
            Found and cleaned up 2 empty switches in `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:328$185'.

            
            Removing empty process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:328$185'.

            
            Found and cleaned up 2 empty switches in `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:338$190'.

            
            Removing empty process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:338$190'.

            
            Found and cleaned up 2 empty switches in `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:354$192'.

            
            Removing empty process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:354$192'.

            
            Found and cleaned up 2 empty switches in `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:363$194'.

            
            Removing empty process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:363$194'.

            
            Found and cleaned up 2 empty switches in `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:372$196'.

            
            Removing empty process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:372$196'.

            
            Found and cleaned up 2 empty switches in `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:386$200'.

            
            Removing empty process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:386$200'.

            
            Found and cleaned up 2 empty switches in `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:397$205'.

            
            Removing empty process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:397$205'.

            
            Found and cleaned up 1 empty switch in `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:413$211'.

            
            Removing empty process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:413$211'.

            
            Found and cleaned up 8 empty switches in `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:418$213'.

            
            Removing empty process `\usb_tx_phy.$proc$rtl/usb_tx_phy.v:418$213'.

            
            Cleaned up 100 empty switches.


            7. Executing OPT pass (performing simple optimizations).


            7.1. Optimizing in-memory representation of design.


            7.2. Executing OPT_CONST pass (perform const folding).


            7.3. Executing OPT_SHARE pass (detect identical cells).

            
            Full command line: opt_share -nomux

            
            Finding identical cells in module `\usb_phy'.

            
            Finding identical cells in module `\usb_rx_phy'.

            
              Cell `$and$rtl/usb_rx_phy.v:167$27' is identical to cell `$and$rtl/usb_rx_phy.v:166$25'.

            
                Redirecting output \Y: $and$rtl/usb_rx_phy.v:167$27_Y = $and$rtl/usb_rx_phy.v:166$25_Y

            
                Removing $and cell `$and$rtl/usb_rx_phy.v:167$27' from module `\usb_rx_phy'.

            
              Cell `$and$rtl/usb_rx_phy.v:172$34' is identical to cell `$and$rtl/usb_rx_phy.v:171$32'.

            
                Redirecting output \Y: $and$rtl/usb_rx_phy.v:172$34_Y = $and$rtl/usb_rx_phy.v:171$32_Y

            
                Removing $and cell `$and$rtl/usb_rx_phy.v:172$34' from module `\usb_rx_phy'.

            
              Cell `$logic_and$rtl/usb_rx_phy.v:220$50' is identical to cell `$logic_and$rtl/usb_rx_phy.v:216$49'.

            
                Redirecting output \Y: $logic_and$rtl/usb_rx_phy.v:220$50_Y = $logic_and$rtl/usb_rx_phy.v:216$49_Y

            
                Removing $logic_and cell `$logic_and$rtl/usb_rx_phy.v:220$50' from module `\usb_rx_phy'.

            
              Cell `$logic_and$rtl/usb_rx_phy.v:224$51' is identical to cell `$logic_and$rtl/usb_rx_phy.v:216$49'.

            
                Redirecting output \Y: $logic_and$rtl/usb_rx_phy.v:224$51_Y = $logic_and$rtl/usb_rx_phy.v:216$49_Y

            
                Removing $logic_and cell `$logic_and$rtl/usb_rx_phy.v:224$51' from module `\usb_rx_phy'.

            
              Cell `$logic_and$rtl/usb_rx_phy.v:227$52' is identical to cell `$logic_and$rtl/usb_rx_phy.v:216$49'.

            
                Redirecting output \Y: $logic_and$rtl/usb_rx_phy.v:227$52_Y = $logic_and$rtl/usb_rx_phy.v:216$49_Y

            
                Removing $logic_and cell `$logic_and$rtl/usb_rx_phy.v:227$52' from module `\usb_rx_phy'.

            
              Cell `$logic_and$rtl/usb_rx_phy.v:285$67' is identical to cell `$logic_and$rtl/usb_rx_phy.v:272$65'.

            
                Redirecting output \Y: $logic_and$rtl/usb_rx_phy.v:285$67_Y = $logic_and$rtl/usb_rx_phy.v:272$65_Y

            
                Removing $logic_and cell `$logic_and$rtl/usb_rx_phy.v:285$67' from module `\usb_rx_phy'.

            
              Cell `$logic_and$rtl/usb_rx_phy.v:294$68' is identical to cell `$logic_and$rtl/usb_rx_phy.v:276$66'.

            
                Redirecting output \Y: $logic_and$rtl/usb_rx_phy.v:294$68_Y = $logic_and$rtl/usb_rx_phy.v:276$66_Y

            
                Removing $logic_and cell `$logic_and$rtl/usb_rx_phy.v:294$68' from module `\usb_rx_phy'.

            
              Cell `$logic_and$rtl/usb_rx_phy.v:303$69' is identical to cell `$logic_and$rtl/usb_rx_phy.v:272$65'.

            
                Redirecting output \Y: $logic_and$rtl/usb_rx_phy.v:303$69_Y = $logic_and$rtl/usb_rx_phy.v:272$65_Y

            
                Removing $logic_and cell `$logic_and$rtl/usb_rx_phy.v:303$69' from module `\usb_rx_phy'.

            
              Cell `$logic_and$rtl/usb_rx_phy.v:312$70' is identical to cell `$logic_and$rtl/usb_rx_phy.v:276$66'.

            
                Redirecting output \Y: $logic_and$rtl/usb_rx_phy.v:312$70_Y = $logic_and$rtl/usb_rx_phy.v:276$66_Y

            
                Removing $logic_and cell `$logic_and$rtl/usb_rx_phy.v:312$70' from module `\usb_rx_phy'.

            
              Cell `$logic_and$rtl/usb_rx_phy.v:314$71' is identical to cell `$logic_and$rtl/usb_rx_phy.v:272$65'.

            
                Redirecting output \Y: $logic_and$rtl/usb_rx_phy.v:314$71_Y = $logic_and$rtl/usb_rx_phy.v:272$65_Y

            
                Removing $logic_and cell `$logic_and$rtl/usb_rx_phy.v:314$71' from module `\usb_rx_phy'.

            
              Cell `$logic_and$rtl/usb_rx_phy.v:327$72' is identical to cell `$logic_and$rtl/usb_rx_phy.v:272$65'.

            
                Redirecting output \Y: $logic_and$rtl/usb_rx_phy.v:327$72_Y = $logic_and$rtl/usb_rx_phy.v:272$65_Y

            
                Removing $logic_and cell `$logic_and$rtl/usb_rx_phy.v:327$72' from module `\usb_rx_phy'.

            
              Cell `$logic_not$rtl/usb_rx_phy.v:176$40' is identical to cell `$logic_not$rtl/usb_rx_phy.v:174$36'.

            
                Redirecting output \Y: $logic_not$rtl/usb_rx_phy.v:176$40_Y = $logic_not$rtl/usb_rx_phy.v:174$36_Y

            
                Removing $logic_not cell `$logic_not$rtl/usb_rx_phy.v:176$40' from module `\usb_rx_phy'.

            
              Cell `$logic_not$rtl/usb_rx_phy.v:176$41' is identical to cell `$logic_not$rtl/usb_rx_phy.v:175$38'.

            
                Redirecting output \Y: $logic_not$rtl/usb_rx_phy.v:176$41_Y = $logic_not$rtl/usb_rx_phy.v:175$38_Y

            
                Removing $logic_not cell `$logic_not$rtl/usb_rx_phy.v:176$41' from module `\usb_rx_phy'.

            
              Cell `$logic_not$rtl/usb_rx_phy.v:260$57' is identical to cell `$logic_not$rtl/usb_rx_phy.v:208$47'.

            
                Redirecting output \Y: $logic_not$rtl/usb_rx_phy.v:260$57_Y = $logic_not$rtl/usb_rx_phy.v:208$47_Y

            
                Removing $logic_not cell `$logic_not$rtl/usb_rx_phy.v:260$57' from module `\usb_rx_phy'.

            
              Cell `$logic_not$rtl/usb_rx_phy.v:268$59' is identical to cell `$logic_not$rtl/usb_rx_phy.v:145$13'.

            
                Redirecting output \Y: $logic_not$rtl/usb_rx_phy.v:268$59_Y = $logic_not$rtl/usb_rx_phy.v:145$13_Y

            
                Removing $logic_not cell `$logic_not$rtl/usb_rx_phy.v:268$59' from module `\usb_rx_phy'.

            
              Cell `$logic_not$rtl/usb_rx_phy.v:352$74' is identical to cell `$logic_not$rtl/usb_rx_phy.v:208$47'.

            
                Redirecting output \Y: $logic_not$rtl/usb_rx_phy.v:352$74_Y = $logic_not$rtl/usb_rx_phy.v:208$47_Y

            
                Removing $logic_not cell `$logic_not$rtl/usb_rx_phy.v:352$74' from module `\usb_rx_phy'.

            
              Cell `$logic_not$rtl/usb_rx_phy.v:376$80' is identical to cell `$logic_not$rtl/usb_rx_phy.v:208$47'.

            
                Redirecting output \Y: $logic_not$rtl/usb_rx_phy.v:376$80_Y = $logic_not$rtl/usb_rx_phy.v:208$47_Y

            
                Removing $logic_not cell `$logic_not$rtl/usb_rx_phy.v:376$80' from module `\usb_rx_phy'.

            
              Cell `$logic_not$rtl/usb_rx_phy.v:378$81' is identical to cell `$logic_not$rtl/usb_rx_phy.v:145$13'.

            
                Redirecting output \Y: $logic_not$rtl/usb_rx_phy.v:378$81_Y = $logic_not$rtl/usb_rx_phy.v:145$13_Y

            
                Removing $logic_not cell `$logic_not$rtl/usb_rx_phy.v:378$81' from module `\usb_rx_phy'.

            
              Cell `$logic_not$rtl/usb_rx_phy.v:392$86' is identical to cell `$logic_not$rtl/usb_rx_phy.v:208$47'.

            
                Redirecting output \Y: $logic_not$rtl/usb_rx_phy.v:392$86_Y = $logic_not$rtl/usb_rx_phy.v:208$47_Y

            
                Removing $logic_not cell `$logic_not$rtl/usb_rx_phy.v:392$86' from module `\usb_rx_phy'.

            
              Cell `$logic_not$rtl/usb_rx_phy.v:404$95' is identical to cell `$logic_not$rtl/usb_rx_phy.v:268$61'.

            
                Redirecting output \Y: $logic_not$rtl/usb_rx_phy.v:404$95_Y = $logic_not$rtl/usb_rx_phy.v:268$61_Y

            
                Removing $logic_not cell `$logic_not$rtl/usb_rx_phy.v:404$95' from module `\usb_rx_phy'.

            
              Cell `$logic_not$rtl/usb_rx_phy.v:428$105' is identical to cell `$logic_not$rtl/usb_rx_phy.v:208$47'.

            
                Redirecting output \Y: $logic_not$rtl/usb_rx_phy.v:428$105_Y = $logic_not$rtl/usb_rx_phy.v:208$47_Y

            
                Removing $logic_not cell `$logic_not$rtl/usb_rx_phy.v:428$105' from module `\usb_rx_phy'.

            
              Cell `$logic_not$rtl/usb_rx_phy.v:430$106' is identical to cell `$logic_not$rtl/usb_rx_phy.v:394$87'.

            
                Redirecting output \Y: $logic_not$rtl/usb_rx_phy.v:430$106_Y = $logic_not$rtl/usb_rx_phy.v:394$87_Y

            
                Removing $logic_not cell `$logic_not$rtl/usb_rx_phy.v:430$106' from module `\usb_rx_phy'.

            
              Cell `$logic_not$rtl/usb_rx_phy.v:432$107' is identical to cell `$logic_not$rtl/usb_rx_phy.v:415$102'.

            
                Redirecting output \Y: $logic_not$rtl/usb_rx_phy.v:432$107_Y = $logic_not$rtl/usb_rx_phy.v:415$102_Y

            
                Removing $logic_not cell `$logic_not$rtl/usb_rx_phy.v:432$107' from module `\usb_rx_phy'.

            
              Cell `$logic_not$rtl/usb_rx_phy.v:439$111' is identical to cell `$logic_not$rtl/usb_rx_phy.v:208$47'.

            
                Redirecting output \Y: $logic_not$rtl/usb_rx_phy.v:439$111_Y = $logic_not$rtl/usb_rx_phy.v:208$47_Y

            
                Removing $logic_not cell `$logic_not$rtl/usb_rx_phy.v:439$111' from module `\usb_rx_phy'.

            
              Cell `$logic_not$rtl/usb_rx_phy.v:441$112' is identical to cell `$logic_not$rtl/usb_rx_phy.v:415$102'.

            
                Redirecting output \Y: $logic_not$rtl/usb_rx_phy.v:441$112_Y = $logic_not$rtl/usb_rx_phy.v:415$102_Y

            
                Removing $logic_not cell `$logic_not$rtl/usb_rx_phy.v:441$112' from module `\usb_rx_phy'.

            
              Cell `$logic_not$rtl/usb_rx_phy.v:443$117' is identical to cell `$logic_not$rtl/usb_rx_phy.v:415$102'.

            
                Redirecting output \Y: $logic_not$rtl/usb_rx_phy.v:443$117_Y = $logic_not$rtl/usb_rx_phy.v:415$102_Y

            
                Removing $logic_not cell `$logic_not$rtl/usb_rx_phy.v:443$117' from module `\usb_rx_phy'.

            
              Cell `$logic_not$rtl/usb_rx_phy.v:445$120' is identical to cell `$logic_not$rtl/usb_rx_phy.v:415$102'.

            
                Redirecting output \Y: $logic_not$rtl/usb_rx_phy.v:445$120_Y = $logic_not$rtl/usb_rx_phy.v:415$102_Y

            
                Removing $logic_not cell `$logic_not$rtl/usb_rx_phy.v:445$120' from module `\usb_rx_phy'.

            
              Cell `$procmux$1039_CMP0' is identical to cell `$procmux$1003_CMP0'.

            
                Redirecting output \Y: $procmux$1039_CMP = $procmux$1003_CMP

            
                Removing $eq cell `$procmux$1039_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$1056_CMP0' is identical to cell `$procmux$1019_CMP0'.

            
                Redirecting output \Y: $procmux$1056_CMP = $procmux$1019_CMP

            
                Removing $eq cell `$procmux$1056_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$1060_CMP0' is identical to cell `$procmux$1023_CMP0'.

            
                Redirecting output \Y: $procmux$1060_CMP = $procmux$1023_CMP

            
                Removing $eq cell `$procmux$1060_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$1064_CMP0' is identical to cell `$procmux$1027_CMP0'.

            
                Redirecting output \Y: $procmux$1064_CMP = $procmux$1027_CMP

            
                Removing $eq cell `$procmux$1064_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$1068_CMP0' is identical to cell `$procmux$1031_CMP0'.

            
                Redirecting output \Y: $procmux$1068_CMP = $procmux$1031_CMP

            
                Removing $eq cell `$procmux$1068_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$1072_CMP0' is identical to cell `$procmux$1035_CMP0'.

            
                Redirecting output \Y: $procmux$1072_CMP = $procmux$1035_CMP

            
                Removing $eq cell `$procmux$1072_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$1076_CMP0' is identical to cell `$procmux$1003_CMP0'.

            
                Redirecting output \Y: $procmux$1076_CMP = $procmux$1003_CMP

            
                Removing $eq cell `$procmux$1076_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$1092_CMP0' is identical to cell `$procmux$1019_CMP0'.

            
                Redirecting output \Y: $procmux$1092_CMP = $procmux$1019_CMP

            
                Removing $eq cell `$procmux$1092_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$1096_CMP0' is identical to cell `$procmux$1023_CMP0'.

            
                Redirecting output \Y: $procmux$1096_CMP = $procmux$1023_CMP

            
                Removing $eq cell `$procmux$1096_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$1100_CMP0' is identical to cell `$procmux$1027_CMP0'.

            
                Redirecting output \Y: $procmux$1100_CMP = $procmux$1027_CMP

            
                Removing $eq cell `$procmux$1100_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$1104_CMP0' is identical to cell `$procmux$1031_CMP0'.

            
                Redirecting output \Y: $procmux$1104_CMP = $procmux$1031_CMP

            
                Removing $eq cell `$procmux$1104_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$1108_CMP0' is identical to cell `$procmux$1035_CMP0'.

            
                Redirecting output \Y: $procmux$1108_CMP = $procmux$1035_CMP

            
                Removing $eq cell `$procmux$1108_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$1112_CMP0' is identical to cell `$procmux$1003_CMP0'.

            
                Redirecting output \Y: $procmux$1112_CMP = $procmux$1003_CMP

            
                Removing $eq cell `$procmux$1112_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$1129_CMP0' is identical to cell `$procmux$1019_CMP0'.

            
                Redirecting output \Y: $procmux$1129_CMP = $procmux$1019_CMP

            
                Removing $eq cell `$procmux$1129_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$1133_CMP0' is identical to cell `$procmux$1023_CMP0'.

            
                Redirecting output \Y: $procmux$1133_CMP = $procmux$1023_CMP

            
                Removing $eq cell `$procmux$1133_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$1137_CMP0' is identical to cell `$procmux$1027_CMP0'.

            
                Redirecting output \Y: $procmux$1137_CMP = $procmux$1027_CMP

            
                Removing $eq cell `$procmux$1137_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$1141_CMP0' is identical to cell `$procmux$1031_CMP0'.

            
                Redirecting output \Y: $procmux$1141_CMP = $procmux$1031_CMP

            
                Removing $eq cell `$procmux$1141_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$1145_CMP0' is identical to cell `$procmux$1035_CMP0'.

            
                Redirecting output \Y: $procmux$1145_CMP = $procmux$1035_CMP

            
                Removing $eq cell `$procmux$1145_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$1149_CMP0' is identical to cell `$procmux$1003_CMP0'.

            
                Redirecting output \Y: $procmux$1149_CMP = $procmux$1003_CMP

            
                Removing $eq cell `$procmux$1149_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$1166_CMP0' is identical to cell `$procmux$1019_CMP0'.

            
                Redirecting output \Y: $procmux$1166_CMP = $procmux$1019_CMP

            
                Removing $eq cell `$procmux$1166_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$1170_CMP0' is identical to cell `$procmux$1023_CMP0'.

            
                Redirecting output \Y: $procmux$1170_CMP = $procmux$1023_CMP

            
                Removing $eq cell `$procmux$1170_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$1174_CMP0' is identical to cell `$procmux$1027_CMP0'.

            
                Redirecting output \Y: $procmux$1174_CMP = $procmux$1027_CMP

            
                Removing $eq cell `$procmux$1174_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$1178_CMP0' is identical to cell `$procmux$1031_CMP0'.

            
                Redirecting output \Y: $procmux$1178_CMP = $procmux$1031_CMP

            
                Removing $eq cell `$procmux$1178_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$1182_CMP0' is identical to cell `$procmux$1035_CMP0'.

            
                Redirecting output \Y: $procmux$1182_CMP = $procmux$1035_CMP

            
                Removing $eq cell `$procmux$1182_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$1186_CMP0' is identical to cell `$procmux$1003_CMP0'.

            
                Redirecting output \Y: $procmux$1186_CMP = $procmux$1003_CMP

            
                Removing $eq cell `$procmux$1186_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$1197_CMP0' is identical to cell `$procmux$1160_CMP0'.

            
                Redirecting output \Y: $procmux$1197_CMP = $procmux$1160_CMP

            
                Removing $eq cell `$procmux$1197_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$1203_CMP0' is identical to cell `$procmux$1019_CMP0'.

            
                Redirecting output \Y: $procmux$1203_CMP = $procmux$1019_CMP

            
                Removing $eq cell `$procmux$1203_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$1207_CMP0' is identical to cell `$procmux$1023_CMP0'.

            
                Redirecting output \Y: $procmux$1207_CMP = $procmux$1023_CMP

            
                Removing $eq cell `$procmux$1207_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$1211_CMP0' is identical to cell `$procmux$1027_CMP0'.

            
                Redirecting output \Y: $procmux$1211_CMP = $procmux$1027_CMP

            
                Removing $eq cell `$procmux$1211_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$1215_CMP0' is identical to cell `$procmux$1031_CMP0'.

            
                Redirecting output \Y: $procmux$1215_CMP = $procmux$1031_CMP

            
                Removing $eq cell `$procmux$1215_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$1219_CMP0' is identical to cell `$procmux$1035_CMP0'.

            
                Redirecting output \Y: $procmux$1219_CMP = $procmux$1035_CMP

            
                Removing $eq cell `$procmux$1219_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$1223_CMP0' is identical to cell `$procmux$1003_CMP0'.

            
                Redirecting output \Y: $procmux$1223_CMP = $procmux$1003_CMP

            
                Removing $eq cell `$procmux$1223_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$1234_CMP0' is identical to cell `$procmux$1160_CMP0'.

            
                Redirecting output \Y: $procmux$1234_CMP = $procmux$1160_CMP

            
                Removing $eq cell `$procmux$1234_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$1240_CMP0' is identical to cell `$procmux$1019_CMP0'.

            
                Redirecting output \Y: $procmux$1240_CMP = $procmux$1019_CMP

            
                Removing $eq cell `$procmux$1240_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$1244_CMP0' is identical to cell `$procmux$1023_CMP0'.

            
                Redirecting output \Y: $procmux$1244_CMP = $procmux$1023_CMP

            
                Removing $eq cell `$procmux$1244_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$1248_CMP0' is identical to cell `$procmux$1027_CMP0'.

            
                Redirecting output \Y: $procmux$1248_CMP = $procmux$1027_CMP

            
                Removing $eq cell `$procmux$1248_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$1252_CMP0' is identical to cell `$procmux$1031_CMP0'.

            
                Redirecting output \Y: $procmux$1252_CMP = $procmux$1031_CMP

            
                Removing $eq cell `$procmux$1252_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$1256_CMP0' is identical to cell `$procmux$1035_CMP0'.

            
                Redirecting output \Y: $procmux$1256_CMP = $procmux$1035_CMP

            
                Removing $eq cell `$procmux$1256_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$1260_CMP0' is identical to cell `$procmux$1003_CMP0'.

            
                Redirecting output \Y: $procmux$1260_CMP = $procmux$1003_CMP

            
                Removing $eq cell `$procmux$1260_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$288_CMP0' is identical to cell `$procmux$273_CMP0'.

            
                Redirecting output \Y: $procmux$288_CMP = $procmux$273_CMP

            
                Removing $eq cell `$procmux$288_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$292_CMP0' is identical to cell `$procmux$277_CMP0'.

            
                Redirecting output \Y: $procmux$292_CMP = $procmux$277_CMP

            
                Removing $eq cell `$procmux$292_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$306_CMP0' is identical to cell `$procmux$277_CMP0'.

            
                Redirecting output \Y: $procmux$306_CMP = $procmux$277_CMP

            
                Removing $eq cell `$procmux$306_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$317_CMP0' is identical to cell `$procmux$273_CMP0'.

            
                Redirecting output \Y: $procmux$317_CMP = $procmux$273_CMP

            
                Removing $eq cell `$procmux$317_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$321_CMP0' is identical to cell `$procmux$277_CMP0'.

            
                Redirecting output \Y: $procmux$321_CMP = $procmux$277_CMP

            
                Removing $eq cell `$procmux$321_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$329_CMP0' is identical to cell `$procmux$284_CMP0'.

            
                Redirecting output \Y: $procmux$329_CMP = $procmux$284_CMP

            
                Removing $eq cell `$procmux$329_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$333_CMP0' is identical to cell `$procmux$273_CMP0'.

            
                Redirecting output \Y: $procmux$333_CMP = $procmux$273_CMP

            
                Removing $eq cell `$procmux$333_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$337_CMP0' is identical to cell `$procmux$277_CMP0'.

            
                Redirecting output \Y: $procmux$337_CMP = $procmux$277_CMP

            
                Removing $eq cell `$procmux$337_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$344_CMP0' is identical to cell `$procmux$284_CMP0'.

            
                Redirecting output \Y: $procmux$344_CMP = $procmux$284_CMP

            
                Removing $eq cell `$procmux$344_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$348_CMP0' is identical to cell `$procmux$273_CMP0'.

            
                Redirecting output \Y: $procmux$348_CMP = $procmux$273_CMP

            
                Removing $eq cell `$procmux$348_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$352_CMP0' is identical to cell `$procmux$277_CMP0'.

            
                Redirecting output \Y: $procmux$352_CMP = $procmux$277_CMP

            
                Removing $eq cell `$procmux$352_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$534_CMP0' is identical to cell `$procmux$1160_CMP0'.

            
                Redirecting output \Y: $procmux$534_CMP = $procmux$1160_CMP

            
                Removing $eq cell `$procmux$534_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$540_CMP0' is identical to cell `$procmux$1019_CMP0'.

            
                Redirecting output \Y: $procmux$540_CMP = $procmux$1019_CMP

            
                Removing $eq cell `$procmux$540_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$544_CMP0' is identical to cell `$procmux$1023_CMP0'.

            
                Redirecting output \Y: $procmux$544_CMP = $procmux$1023_CMP

            
                Removing $eq cell `$procmux$544_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$548_CMP0' is identical to cell `$procmux$1027_CMP0'.

            
                Redirecting output \Y: $procmux$548_CMP = $procmux$1027_CMP

            
                Removing $eq cell `$procmux$548_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$552_CMP0' is identical to cell `$procmux$1031_CMP0'.

            
                Redirecting output \Y: $procmux$552_CMP = $procmux$1031_CMP

            
                Removing $eq cell `$procmux$552_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$556_CMP0' is identical to cell `$procmux$1035_CMP0'.

            
                Redirecting output \Y: $procmux$556_CMP = $procmux$1035_CMP

            
                Removing $eq cell `$procmux$556_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$560_CMP0' is identical to cell `$procmux$1003_CMP0'.

            
                Redirecting output \Y: $procmux$560_CMP = $procmux$1003_CMP

            
                Removing $eq cell `$procmux$560_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$570_CMP0' is identical to cell `$procmux$1160_CMP0'.

            
                Redirecting output \Y: $procmux$570_CMP = $procmux$1160_CMP

            
                Removing $eq cell `$procmux$570_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$576_CMP0' is identical to cell `$procmux$1019_CMP0'.

            
                Redirecting output \Y: $procmux$576_CMP = $procmux$1019_CMP

            
                Removing $eq cell `$procmux$576_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$580_CMP0' is identical to cell `$procmux$1023_CMP0'.

            
                Redirecting output \Y: $procmux$580_CMP = $procmux$1023_CMP

            
                Removing $eq cell `$procmux$580_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$584_CMP0' is identical to cell `$procmux$1027_CMP0'.

            
                Redirecting output \Y: $procmux$584_CMP = $procmux$1027_CMP

            
                Removing $eq cell `$procmux$584_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$588_CMP0' is identical to cell `$procmux$1031_CMP0'.

            
                Redirecting output \Y: $procmux$588_CMP = $procmux$1031_CMP

            
                Removing $eq cell `$procmux$588_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$592_CMP0' is identical to cell `$procmux$1035_CMP0'.

            
                Redirecting output \Y: $procmux$592_CMP = $procmux$1035_CMP

            
                Removing $eq cell `$procmux$592_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$596_CMP0' is identical to cell `$procmux$1003_CMP0'.

            
                Redirecting output \Y: $procmux$596_CMP = $procmux$1003_CMP

            
                Removing $eq cell `$procmux$596_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$606_CMP0' is identical to cell `$procmux$1160_CMP0'.

            
                Redirecting output \Y: $procmux$606_CMP = $procmux$1160_CMP

            
                Removing $eq cell `$procmux$606_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$612_CMP0' is identical to cell `$procmux$1019_CMP0'.

            
                Redirecting output \Y: $procmux$612_CMP = $procmux$1019_CMP

            
                Removing $eq cell `$procmux$612_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$616_CMP0' is identical to cell `$procmux$1023_CMP0'.

            
                Redirecting output \Y: $procmux$616_CMP = $procmux$1023_CMP

            
                Removing $eq cell `$procmux$616_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$620_CMP0' is identical to cell `$procmux$1027_CMP0'.

            
                Redirecting output \Y: $procmux$620_CMP = $procmux$1027_CMP

            
                Removing $eq cell `$procmux$620_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$624_CMP0' is identical to cell `$procmux$1031_CMP0'.

            
                Redirecting output \Y: $procmux$624_CMP = $procmux$1031_CMP

            
                Removing $eq cell `$procmux$624_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$628_CMP0' is identical to cell `$procmux$1035_CMP0'.

            
                Redirecting output \Y: $procmux$628_CMP = $procmux$1035_CMP

            
                Removing $eq cell `$procmux$628_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$632_CMP0' is identical to cell `$procmux$1003_CMP0'.

            
                Redirecting output \Y: $procmux$632_CMP = $procmux$1003_CMP

            
                Removing $eq cell `$procmux$632_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$663_CMP0' is identical to cell `$procmux$1003_CMP0'.

            
                Redirecting output \Y: $procmux$663_CMP = $procmux$1003_CMP

            
                Removing $eq cell `$procmux$663_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$691_CMP0' is identical to cell `$procmux$1035_CMP0'.

            
                Redirecting output \Y: $procmux$691_CMP = $procmux$1035_CMP

            
                Removing $eq cell `$procmux$691_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$695_CMP0' is identical to cell `$procmux$1003_CMP0'.

            
                Redirecting output \Y: $procmux$695_CMP = $procmux$1003_CMP

            
                Removing $eq cell `$procmux$695_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$723_CMP0' is identical to cell `$procmux$1035_CMP0'.

            
                Redirecting output \Y: $procmux$723_CMP = $procmux$1035_CMP

            
                Removing $eq cell `$procmux$723_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$727_CMP0' is identical to cell `$procmux$1003_CMP0'.

            
                Redirecting output \Y: $procmux$727_CMP = $procmux$1003_CMP

            
                Removing $eq cell `$procmux$727_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$752_CMP0' is identical to cell `$procmux$1031_CMP0'.

            
                Redirecting output \Y: $procmux$752_CMP = $procmux$1031_CMP

            
                Removing $eq cell `$procmux$752_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$756_CMP0' is identical to cell `$procmux$1035_CMP0'.

            
                Redirecting output \Y: $procmux$756_CMP = $procmux$1035_CMP

            
                Removing $eq cell `$procmux$756_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$760_CMP0' is identical to cell `$procmux$1003_CMP0'.

            
                Redirecting output \Y: $procmux$760_CMP = $procmux$1003_CMP

            
                Removing $eq cell `$procmux$760_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$785_CMP0' is identical to cell `$procmux$1031_CMP0'.

            
                Redirecting output \Y: $procmux$785_CMP = $procmux$1031_CMP

            
                Removing $eq cell `$procmux$785_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$789_CMP0' is identical to cell `$procmux$1035_CMP0'.

            
                Redirecting output \Y: $procmux$789_CMP = $procmux$1035_CMP

            
                Removing $eq cell `$procmux$789_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$793_CMP0' is identical to cell `$procmux$1003_CMP0'.

            
                Redirecting output \Y: $procmux$793_CMP = $procmux$1003_CMP

            
                Removing $eq cell `$procmux$793_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$815_CMP0' is identical to cell `$procmux$1027_CMP0'.

            
                Redirecting output \Y: $procmux$815_CMP = $procmux$1027_CMP

            
                Removing $eq cell `$procmux$815_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$819_CMP0' is identical to cell `$procmux$1031_CMP0'.

            
                Redirecting output \Y: $procmux$819_CMP = $procmux$1031_CMP

            
                Removing $eq cell `$procmux$819_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$823_CMP0' is identical to cell `$procmux$1035_CMP0'.

            
                Redirecting output \Y: $procmux$823_CMP = $procmux$1035_CMP

            
                Removing $eq cell `$procmux$823_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$827_CMP0' is identical to cell `$procmux$1003_CMP0'.

            
                Redirecting output \Y: $procmux$827_CMP = $procmux$1003_CMP

            
                Removing $eq cell `$procmux$827_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$849_CMP0' is identical to cell `$procmux$1027_CMP0'.

            
                Redirecting output \Y: $procmux$849_CMP = $procmux$1027_CMP

            
                Removing $eq cell `$procmux$849_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$853_CMP0' is identical to cell `$procmux$1031_CMP0'.

            
                Redirecting output \Y: $procmux$853_CMP = $procmux$1031_CMP

            
                Removing $eq cell `$procmux$853_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$857_CMP0' is identical to cell `$procmux$1035_CMP0'.

            
                Redirecting output \Y: $procmux$857_CMP = $procmux$1035_CMP

            
                Removing $eq cell `$procmux$857_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$861_CMP0' is identical to cell `$procmux$1003_CMP0'.

            
                Redirecting output \Y: $procmux$861_CMP = $procmux$1003_CMP

            
                Removing $eq cell `$procmux$861_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$880_CMP0' is identical to cell `$procmux$1023_CMP0'.

            
                Redirecting output \Y: $procmux$880_CMP = $procmux$1023_CMP

            
                Removing $eq cell `$procmux$880_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$884_CMP0' is identical to cell `$procmux$1027_CMP0'.

            
                Redirecting output \Y: $procmux$884_CMP = $procmux$1027_CMP

            
                Removing $eq cell `$procmux$884_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$888_CMP0' is identical to cell `$procmux$1031_CMP0'.

            
                Redirecting output \Y: $procmux$888_CMP = $procmux$1031_CMP

            
                Removing $eq cell `$procmux$888_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$892_CMP0' is identical to cell `$procmux$1035_CMP0'.

            
                Redirecting output \Y: $procmux$892_CMP = $procmux$1035_CMP

            
                Removing $eq cell `$procmux$892_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$896_CMP0' is identical to cell `$procmux$1003_CMP0'.

            
                Redirecting output \Y: $procmux$896_CMP = $procmux$1003_CMP

            
                Removing $eq cell `$procmux$896_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$915_CMP0' is identical to cell `$procmux$1023_CMP0'.

            
                Redirecting output \Y: $procmux$915_CMP = $procmux$1023_CMP

            
                Removing $eq cell `$procmux$915_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$919_CMP0' is identical to cell `$procmux$1027_CMP0'.

            
                Redirecting output \Y: $procmux$919_CMP = $procmux$1027_CMP

            
                Removing $eq cell `$procmux$919_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$923_CMP0' is identical to cell `$procmux$1031_CMP0'.

            
                Redirecting output \Y: $procmux$923_CMP = $procmux$1031_CMP

            
                Removing $eq cell `$procmux$923_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$927_CMP0' is identical to cell `$procmux$1035_CMP0'.

            
                Redirecting output \Y: $procmux$927_CMP = $procmux$1035_CMP

            
                Removing $eq cell `$procmux$927_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$931_CMP0' is identical to cell `$procmux$1003_CMP0'.

            
                Redirecting output \Y: $procmux$931_CMP = $procmux$1003_CMP

            
                Removing $eq cell `$procmux$931_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$947_CMP0' is identical to cell `$procmux$1019_CMP0'.

            
                Redirecting output \Y: $procmux$947_CMP = $procmux$1019_CMP

            
                Removing $eq cell `$procmux$947_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$951_CMP0' is identical to cell `$procmux$1023_CMP0'.

            
                Redirecting output \Y: $procmux$951_CMP = $procmux$1023_CMP

            
                Removing $eq cell `$procmux$951_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$955_CMP0' is identical to cell `$procmux$1027_CMP0'.

            
                Redirecting output \Y: $procmux$955_CMP = $procmux$1027_CMP

            
                Removing $eq cell `$procmux$955_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$959_CMP0' is identical to cell `$procmux$1031_CMP0'.

            
                Redirecting output \Y: $procmux$959_CMP = $procmux$1031_CMP

            
                Removing $eq cell `$procmux$959_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$963_CMP0' is identical to cell `$procmux$1035_CMP0'.

            
                Redirecting output \Y: $procmux$963_CMP = $procmux$1035_CMP

            
                Removing $eq cell `$procmux$963_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$967_CMP0' is identical to cell `$procmux$1003_CMP0'.

            
                Redirecting output \Y: $procmux$967_CMP = $procmux$1003_CMP

            
                Removing $eq cell `$procmux$967_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$983_CMP0' is identical to cell `$procmux$1019_CMP0'.

            
                Redirecting output \Y: $procmux$983_CMP = $procmux$1019_CMP

            
                Removing $eq cell `$procmux$983_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$987_CMP0' is identical to cell `$procmux$1023_CMP0'.

            
                Redirecting output \Y: $procmux$987_CMP = $procmux$1023_CMP

            
                Removing $eq cell `$procmux$987_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$991_CMP0' is identical to cell `$procmux$1027_CMP0'.

            
                Redirecting output \Y: $procmux$991_CMP = $procmux$1027_CMP

            
                Removing $eq cell `$procmux$991_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$995_CMP0' is identical to cell `$procmux$1031_CMP0'.

            
                Redirecting output \Y: $procmux$995_CMP = $procmux$1031_CMP

            
                Removing $eq cell `$procmux$995_CMP0' from module `\usb_rx_phy'.

            
              Cell `$procmux$999_CMP0' is identical to cell `$procmux$1035_CMP0'.

            
                Redirecting output \Y: $procmux$999_CMP = $procmux$1035_CMP

            
                Removing $eq cell `$procmux$999_CMP0' from module `\usb_rx_phy'.

            
              Cell `$logic_and$rtl/usb_rx_phy.v:441$113' is identical to cell `$logic_and$rtl/usb_rx_phy.v:432$108'.

            
                Redirecting output \Y: $logic_and$rtl/usb_rx_phy.v:441$113_Y = $logic_and$rtl/usb_rx_phy.v:432$108_Y

            
                Removing $logic_and cell `$logic_and$rtl/usb_rx_phy.v:441$113' from module `\usb_rx_phy'.

            
            Finding identical cells in module `\usb_tx_phy'.

            
              Cell `$logic_not$rtl/usb_tx_phy.v:166$135' is identical to cell `$logic_not$rtl/usb_tx_phy.v:151$131'.

            
                Redirecting output \Y: $logic_not$rtl/usb_tx_phy.v:166$135_Y = $logic_not$rtl/usb_tx_phy.v:151$131_Y

            
                Removing $logic_not cell `$logic_not$rtl/usb_tx_phy.v:166$135' from module `\usb_tx_phy'.

            
              Cell `$logic_not$rtl/usb_tx_phy.v:177$137' is identical to cell `$logic_not$rtl/usb_tx_phy.v:151$131'.

            
                Redirecting output \Y: $logic_not$rtl/usb_tx_phy.v:177$137_Y = $logic_not$rtl/usb_tx_phy.v:151$131_Y

            
                Removing $logic_not cell `$logic_not$rtl/usb_tx_phy.v:177$137' from module `\usb_tx_phy'.

            
              Cell `$logic_not$rtl/usb_tx_phy.v:190$139' is identical to cell `$logic_not$rtl/usb_tx_phy.v:151$131'.

            
                Redirecting output \Y: $logic_not$rtl/usb_tx_phy.v:190$139_Y = $logic_not$rtl/usb_tx_phy.v:151$131_Y

            
                Removing $logic_not cell `$logic_not$rtl/usb_tx_phy.v:190$139' from module `\usb_tx_phy'.

            
              Cell `$logic_not$rtl/usb_tx_phy.v:206$144' is identical to cell `$logic_not$rtl/usb_tx_phy.v:151$131'.

            
                Redirecting output \Y: $logic_not$rtl/usb_tx_phy.v:206$144_Y = $logic_not$rtl/usb_tx_phy.v:151$131_Y

            
                Removing $logic_not cell `$logic_not$rtl/usb_tx_phy.v:206$144' from module `\usb_tx_phy'.

            
              Cell `$logic_not$rtl/usb_tx_phy.v:215$150' is identical to cell `$logic_not$rtl/usb_tx_phy.v:208$145'.

            
                Redirecting output \Y: $logic_not$rtl/usb_tx_phy.v:215$150_Y = $logic_not$rtl/usb_tx_phy.v:208$145_Y

            
                Removing $logic_not cell `$logic_not$rtl/usb_tx_phy.v:215$150' from module `\usb_tx_phy'.

            
              Cell `$logic_not$rtl/usb_tx_phy.v:229$152' is identical to cell `$logic_not$rtl/usb_tx_phy.v:210$146'.

            
                Redirecting output \Y: $logic_not$rtl/usb_tx_phy.v:229$152_Y = $logic_not$rtl/usb_tx_phy.v:210$146_Y

            
                Removing $logic_not cell `$logic_not$rtl/usb_tx_phy.v:229$152' from module `\usb_tx_phy'.

            
              Cell `$logic_not$rtl/usb_tx_phy.v:254$161' is identical to cell `$logic_not$rtl/usb_tx_phy.v:151$131'.

            
                Redirecting output \Y: $logic_not$rtl/usb_tx_phy.v:254$161_Y = $logic_not$rtl/usb_tx_phy.v:151$131_Y

            
                Removing $logic_not cell `$logic_not$rtl/usb_tx_phy.v:254$161' from module `\usb_tx_phy'.

            
              Cell `$logic_not$rtl/usb_tx_phy.v:256$162' is identical to cell `$logic_not$rtl/usb_tx_phy.v:208$145'.

            
                Redirecting output \Y: $logic_not$rtl/usb_tx_phy.v:256$162_Y = $logic_not$rtl/usb_tx_phy.v:208$145_Y

            
                Removing $logic_not cell `$logic_not$rtl/usb_tx_phy.v:256$162' from module `\usb_tx_phy'.

            
              Cell `$logic_not$rtl/usb_tx_phy.v:271$168' is identical to cell `$logic_not$rtl/usb_tx_phy.v:151$131'.

            
                Redirecting output \Y: $logic_not$rtl/usb_tx_phy.v:271$168_Y = $logic_not$rtl/usb_tx_phy.v:151$131_Y

            
                Removing $logic_not cell `$logic_not$rtl/usb_tx_phy.v:271$168' from module `\usb_tx_phy'.

            
              Cell `$logic_not$rtl/usb_tx_phy.v:273$169' is identical to cell `$logic_not$rtl/usb_tx_phy.v:208$145'.

            
                Redirecting output \Y: $logic_not$rtl/usb_tx_phy.v:273$169_Y = $logic_not$rtl/usb_tx_phy.v:208$145_Y

            
                Removing $logic_not cell `$logic_not$rtl/usb_tx_phy.v:273$169' from module `\usb_tx_phy'.

            
              Cell `$logic_not$rtl/usb_tx_phy.v:285$173' is identical to cell `$logic_not$rtl/usb_tx_phy.v:151$131'.

            
                Redirecting output \Y: $logic_not$rtl/usb_tx_phy.v:285$173_Y = $logic_not$rtl/usb_tx_phy.v:151$131_Y

            
                Removing $logic_not cell `$logic_not$rtl/usb_tx_phy.v:285$173' from module `\usb_tx_phy'.

            
              Cell `$logic_not$rtl/usb_tx_phy.v:287$174' is identical to cell `$logic_not$rtl/usb_tx_phy.v:208$145'.

            
                Redirecting output \Y: $logic_not$rtl/usb_tx_phy.v:287$174_Y = $logic_not$rtl/usb_tx_phy.v:208$145_Y

            
                Removing $logic_not cell `$logic_not$rtl/usb_tx_phy.v:287$174' from module `\usb_tx_phy'.

            
              Cell `$logic_not$rtl/usb_tx_phy.v:301$180' is identical to cell `$logic_not$rtl/usb_tx_phy.v:151$131'.

            
                Redirecting output \Y: $logic_not$rtl/usb_tx_phy.v:301$180_Y = $logic_not$rtl/usb_tx_phy.v:151$131_Y

            
                Removing $logic_not cell `$logic_not$rtl/usb_tx_phy.v:301$180' from module `\usb_tx_phy'.

            
              Cell `$logic_not$rtl/usb_tx_phy.v:312$182' is identical to cell `$logic_not$rtl/usb_tx_phy.v:151$131'.

            
                Redirecting output \Y: $logic_not$rtl/usb_tx_phy.v:312$182_Y = $logic_not$rtl/usb_tx_phy.v:151$131_Y

            
                Removing $logic_not cell `$logic_not$rtl/usb_tx_phy.v:312$182' from module `\usb_tx_phy'.

            
              Cell `$logic_not$rtl/usb_tx_phy.v:321$184' is identical to cell `$logic_not$rtl/usb_tx_phy.v:151$131'.

            
                Redirecting output \Y: $logic_not$rtl/usb_tx_phy.v:321$184_Y = $logic_not$rtl/usb_tx_phy.v:151$131_Y

            
                Removing $logic_not cell `$logic_not$rtl/usb_tx_phy.v:321$184' from module `\usb_tx_phy'.

            
              Cell `$logic_not$rtl/usb_tx_phy.v:330$186' is identical to cell `$logic_not$rtl/usb_tx_phy.v:151$131'.

            
                Redirecting output \Y: $logic_not$rtl/usb_tx_phy.v:330$186_Y = $logic_not$rtl/usb_tx_phy.v:151$131_Y

            
                Removing $logic_not cell `$logic_not$rtl/usb_tx_phy.v:330$186' from module `\usb_tx_phy'.

            
              Cell `$logic_not$rtl/usb_tx_phy.v:340$191' is identical to cell `$logic_not$rtl/usb_tx_phy.v:151$131'.

            
                Redirecting output \Y: $logic_not$rtl/usb_tx_phy.v:340$191_Y = $logic_not$rtl/usb_tx_phy.v:151$131_Y

            
                Removing $logic_not cell `$logic_not$rtl/usb_tx_phy.v:340$191' from module `\usb_tx_phy'.

            
              Cell `$logic_not$rtl/usb_tx_phy.v:356$193' is identical to cell `$logic_not$rtl/usb_tx_phy.v:151$131'.

            
                Redirecting output \Y: $logic_not$rtl/usb_tx_phy.v:356$193_Y = $logic_not$rtl/usb_tx_phy.v:151$131_Y

            
                Removing $logic_not cell `$logic_not$rtl/usb_tx_phy.v:356$193' from module `\usb_tx_phy'.

            
              Cell `$logic_not$rtl/usb_tx_phy.v:365$195' is identical to cell `$logic_not$rtl/usb_tx_phy.v:151$131'.

            
                Redirecting output \Y: $logic_not$rtl/usb_tx_phy.v:365$195_Y = $logic_not$rtl/usb_tx_phy.v:151$131_Y

            
                Removing $logic_not cell `$logic_not$rtl/usb_tx_phy.v:365$195' from module `\usb_tx_phy'.

            
              Cell `$logic_not$rtl/usb_tx_phy.v:374$197' is identical to cell `$logic_not$rtl/usb_tx_phy.v:151$131'.

            
                Redirecting output \Y: $logic_not$rtl/usb_tx_phy.v:374$197_Y = $logic_not$rtl/usb_tx_phy.v:151$131_Y

            
                Removing $logic_not cell `$logic_not$rtl/usb_tx_phy.v:374$197' from module `\usb_tx_phy'.

            
              Cell `$logic_not$rtl/usb_tx_phy.v:388$201' is identical to cell `$logic_not$rtl/usb_tx_phy.v:151$131'.

            
                Redirecting output \Y: $logic_not$rtl/usb_tx_phy.v:388$201_Y = $logic_not$rtl/usb_tx_phy.v:151$131_Y

            
                Removing $logic_not cell `$logic_not$rtl/usb_tx_phy.v:388$201' from module `\usb_tx_phy'.

            
              Cell `$logic_not$rtl/usb_tx_phy.v:399$206' is identical to cell `$logic_not$rtl/usb_tx_phy.v:151$131'.

            
                Redirecting output \Y: $logic_not$rtl/usb_tx_phy.v:399$206_Y = $logic_not$rtl/usb_tx_phy.v:151$131_Y

            
                Removing $logic_not cell `$logic_not$rtl/usb_tx_phy.v:399$206' from module `\usb_tx_phy'.

            
              Cell `$logic_not$rtl/usb_tx_phy.v:402$207' is identical to cell `$logic_not$rtl/usb_tx_phy.v:391$202'.

            
                Redirecting output \Y: $logic_not$rtl/usb_tx_phy.v:402$207_Y = $logic_not$rtl/usb_tx_phy.v:391$202_Y

            
                Removing $logic_not cell `$logic_not$rtl/usb_tx_phy.v:402$207' from module `\usb_tx_phy'.

            
              Cell `$logic_not$rtl/usb_tx_phy.v:415$212' is identical to cell `$logic_not$rtl/usb_tx_phy.v:151$131'.

            
                Redirecting output \Y: $logic_not$rtl/usb_tx_phy.v:415$212_Y = $logic_not$rtl/usb_tx_phy.v:151$131_Y

            
                Removing $logic_not cell `$logic_not$rtl/usb_tx_phy.v:415$212' from module `\usb_tx_phy'.

            
              Cell `$logic_not$rtl/usb_tx_phy.v:458$217' is identical to cell `$logic_not$rtl/usb_tx_phy.v:391$202'.

            
                Redirecting output \Y: $logic_not$rtl/usb_tx_phy.v:458$217_Y = $logic_not$rtl/usb_tx_phy.v:391$202_Y

            
                Removing $logic_not cell `$logic_not$rtl/usb_tx_phy.v:458$217' from module `\usb_tx_phy'.

            
              Cell `$not$rtl/usb_tx_phy.v:402$208' is identical to cell `$not$rtl/usb_tx_phy.v:289$177'.

            
                Redirecting output \Y: $not$rtl/usb_tx_phy.v:402$208_Y = $not$rtl/usb_tx_phy.v:289$177_Y

            
                Removing $not cell `$not$rtl/usb_tx_phy.v:402$208' from module `\usb_tx_phy'.

            
              Cell `$procmux$1616_CMP0' is identical to cell `$procmux$1593_CMP0'.

            
                Redirecting output \Y: $procmux$1616_CMP = $procmux$1593_CMP

            
                Removing $eq cell `$procmux$1616_CMP0' from module `\usb_tx_phy'.

            
              Cell `$procmux$1620_CMP0' is identical to cell `$procmux$1597_CMP0'.

            
                Redirecting output \Y: $procmux$1620_CMP = $procmux$1597_CMP

            
                Removing $eq cell `$procmux$1620_CMP0' from module `\usb_tx_phy'.

            
              Cell `$procmux$1624_CMP0' is identical to cell `$procmux$1601_CMP0'.

            
                Redirecting output \Y: $procmux$1624_CMP = $procmux$1601_CMP

            
                Removing $eq cell `$procmux$1624_CMP0' from module `\usb_tx_phy'.

            
              Cell `$procmux$1639_CMP0' is identical to cell `$procmux$1593_CMP0'.

            
                Redirecting output \Y: $procmux$1639_CMP = $procmux$1593_CMP

            
                Removing $eq cell `$procmux$1639_CMP0' from module `\usb_tx_phy'.

            
              Cell `$procmux$1643_CMP0' is identical to cell `$procmux$1597_CMP0'.

            
                Redirecting output \Y: $procmux$1643_CMP = $procmux$1597_CMP

            
                Removing $eq cell `$procmux$1643_CMP0' from module `\usb_tx_phy'.

            
              Cell `$procmux$1647_CMP0' is identical to cell `$procmux$1601_CMP0'.

            
                Redirecting output \Y: $procmux$1647_CMP = $procmux$1601_CMP

            
                Removing $eq cell `$procmux$1647_CMP0' from module `\usb_tx_phy'.

            
              Cell `$procmux$1668_CMP0' is identical to cell `$procmux$1601_CMP0'.

            
                Redirecting output \Y: $procmux$1668_CMP = $procmux$1601_CMP

            
                Removing $eq cell `$procmux$1668_CMP0' from module `\usb_tx_phy'.

            
              Cell `$procmux$1685_CMP0' is identical to cell `$procmux$1593_CMP0'.

            
                Redirecting output \Y: $procmux$1685_CMP = $procmux$1593_CMP

            
                Removing $eq cell `$procmux$1685_CMP0' from module `\usb_tx_phy'.

            
              Cell `$procmux$1689_CMP0' is identical to cell `$procmux$1597_CMP0'.

            
                Redirecting output \Y: $procmux$1689_CMP = $procmux$1597_CMP

            
                Removing $eq cell `$procmux$1689_CMP0' from module `\usb_tx_phy'.

            
              Cell `$procmux$1693_CMP0' is identical to cell `$procmux$1601_CMP0'.

            
                Redirecting output \Y: $procmux$1693_CMP = $procmux$1601_CMP

            
                Removing $eq cell `$procmux$1693_CMP0' from module `\usb_tx_phy'.

            
              Cell `$procmux$1715_CMP0' is identical to cell `$procmux$1601_CMP0'.

            
                Redirecting output \Y: $procmux$1715_CMP = $procmux$1601_CMP

            
                Removing $eq cell `$procmux$1715_CMP0' from module `\usb_tx_phy'.

            
              Cell `$procmux$1737_CMP0' is identical to cell `$procmux$1601_CMP0'.

            
                Redirecting output \Y: $procmux$1737_CMP = $procmux$1601_CMP

            
                Removing $eq cell `$procmux$1737_CMP0' from module `\usb_tx_phy'.

            
              Cell `$procmux$1756_CMP0' is identical to cell `$procmux$1597_CMP0'.

            
                Redirecting output \Y: $procmux$1756_CMP = $procmux$1597_CMP

            
                Removing $eq cell `$procmux$1756_CMP0' from module `\usb_tx_phy'.

            
              Cell `$procmux$1760_CMP0' is identical to cell `$procmux$1601_CMP0'.

            
                Redirecting output \Y: $procmux$1760_CMP = $procmux$1601_CMP

            
                Removing $eq cell `$procmux$1760_CMP0' from module `\usb_tx_phy'.

            
              Cell `$procmux$1779_CMP0' is identical to cell `$procmux$1597_CMP0'.

            
                Redirecting output \Y: $procmux$1779_CMP = $procmux$1597_CMP

            
                Removing $eq cell `$procmux$1779_CMP0' from module `\usb_tx_phy'.

            
              Cell `$procmux$1783_CMP0' is identical to cell `$procmux$1601_CMP0'.

            
                Redirecting output \Y: $procmux$1783_CMP = $procmux$1601_CMP

            
                Removing $eq cell `$procmux$1783_CMP0' from module `\usb_tx_phy'.

            
              Cell `$procmux$1802_CMP0' is identical to cell `$procmux$1597_CMP0'.

            
                Redirecting output \Y: $procmux$1802_CMP = $procmux$1597_CMP

            
                Removing $eq cell `$procmux$1802_CMP0' from module `\usb_tx_phy'.

            
              Cell `$procmux$1806_CMP0' is identical to cell `$procmux$1601_CMP0'.

            
                Redirecting output \Y: $procmux$1806_CMP = $procmux$1601_CMP

            
                Removing $eq cell `$procmux$1806_CMP0' from module `\usb_tx_phy'.

            
              Cell `$procmux$1822_CMP0' is identical to cell `$procmux$1593_CMP0'.

            
                Redirecting output \Y: $procmux$1822_CMP = $procmux$1593_CMP

            
                Removing $eq cell `$procmux$1822_CMP0' from module `\usb_tx_phy'.

            
              Cell `$procmux$1826_CMP0' is identical to cell `$procmux$1597_CMP0'.

            
                Redirecting output \Y: $procmux$1826_CMP = $procmux$1597_CMP

            
                Removing $eq cell `$procmux$1826_CMP0' from module `\usb_tx_phy'.

            
              Cell `$procmux$1830_CMP0' is identical to cell `$procmux$1601_CMP0'.

            
                Redirecting output \Y: $procmux$1830_CMP = $procmux$1601_CMP

            
                Removing $eq cell `$procmux$1830_CMP0' from module `\usb_tx_phy'.

            
              Cell `$procmux$1846_CMP0' is identical to cell `$procmux$1593_CMP0'.

            
                Redirecting output \Y: $procmux$1846_CMP = $procmux$1593_CMP

            
                Removing $eq cell `$procmux$1846_CMP0' from module `\usb_tx_phy'.

            
              Cell `$procmux$1850_CMP0' is identical to cell `$procmux$1597_CMP0'.

            
                Redirecting output \Y: $procmux$1850_CMP = $procmux$1597_CMP

            
                Removing $eq cell `$procmux$1850_CMP0' from module `\usb_tx_phy'.

            
              Cell `$procmux$1854_CMP0' is identical to cell `$procmux$1601_CMP0'.

            
                Redirecting output \Y: $procmux$1854_CMP = $procmux$1601_CMP

            
                Removing $eq cell `$procmux$1854_CMP0' from module `\usb_tx_phy'.

            
              Cell `$procmux$1870_CMP0' is identical to cell `$procmux$1593_CMP0'.

            
                Redirecting output \Y: $procmux$1870_CMP = $procmux$1593_CMP

            
                Removing $eq cell `$procmux$1870_CMP0' from module `\usb_tx_phy'.

            
              Cell `$procmux$1874_CMP0' is identical to cell `$procmux$1597_CMP0'.

            
                Redirecting output \Y: $procmux$1874_CMP = $procmux$1597_CMP

            
                Removing $eq cell `$procmux$1874_CMP0' from module `\usb_tx_phy'.

            
              Cell `$procmux$1878_CMP0' is identical to cell `$procmux$1601_CMP0'.

            
                Redirecting output \Y: $procmux$1878_CMP = $procmux$1601_CMP

            
                Removing $eq cell `$procmux$1878_CMP0' from module `\usb_tx_phy'.

            
              Cell `$procmux$1894_CMP0' is identical to cell `$procmux$1593_CMP0'.

            
                Redirecting output \Y: $procmux$1894_CMP = $procmux$1593_CMP

            
                Removing $eq cell `$procmux$1894_CMP0' from module `\usb_tx_phy'.

            
              Cell `$procmux$1898_CMP0' is identical to cell `$procmux$1597_CMP0'.

            
                Redirecting output \Y: $procmux$1898_CMP = $procmux$1597_CMP

            
                Removing $eq cell `$procmux$1898_CMP0' from module `\usb_tx_phy'.

            
              Cell `$procmux$1902_CMP0' is identical to cell `$procmux$1601_CMP0'.

            
                Redirecting output \Y: $procmux$1902_CMP = $procmux$1601_CMP

            
                Removing $eq cell `$procmux$1902_CMP0' from module `\usb_tx_phy'.

            
              Cell `$procmux$1913_CMP0' is identical to cell `$procmux$1679_CMP0'.

            
                Redirecting output \Y: $procmux$1913_CMP = $procmux$1679_CMP

            
                Removing $eq cell `$procmux$1913_CMP0' from module `\usb_tx_phy'.

            
              Cell `$procmux$1919_CMP0' is identical to cell `$procmux$1593_CMP0'.

            
                Redirecting output \Y: $procmux$1919_CMP = $procmux$1593_CMP

            
                Removing $eq cell `$procmux$1919_CMP0' from module `\usb_tx_phy'.

            
              Cell `$procmux$1923_CMP0' is identical to cell `$procmux$1597_CMP0'.

            
                Redirecting output \Y: $procmux$1923_CMP = $procmux$1597_CMP

            
                Removing $eq cell `$procmux$1923_CMP0' from module `\usb_tx_phy'.

            
              Cell `$procmux$1927_CMP0' is identical to cell `$procmux$1601_CMP0'.

            
                Redirecting output \Y: $procmux$1927_CMP = $procmux$1601_CMP

            
                Removing $eq cell `$procmux$1927_CMP0' from module `\usb_tx_phy'.

            
              Cell `$procmux$1935_CMP0' is identical to cell `$procmux$1675_CMP0'.

            
                Redirecting output \Y: $procmux$1935_CMP = $procmux$1675_CMP

            
                Removing $eq cell `$procmux$1935_CMP0' from module `\usb_tx_phy'.

            
              Cell `$procmux$1939_CMP0' is identical to cell `$procmux$1679_CMP0'.

            
                Redirecting output \Y: $procmux$1939_CMP = $procmux$1679_CMP

            
                Removing $eq cell `$procmux$1939_CMP0' from module `\usb_tx_phy'.

            
              Cell `$procmux$1945_CMP0' is identical to cell `$procmux$1593_CMP0'.

            
                Redirecting output \Y: $procmux$1945_CMP = $procmux$1593_CMP

            
                Removing $eq cell `$procmux$1945_CMP0' from module `\usb_tx_phy'.

            
              Cell `$procmux$1949_CMP0' is identical to cell `$procmux$1597_CMP0'.

            
                Redirecting output \Y: $procmux$1949_CMP = $procmux$1597_CMP

            
                Removing $eq cell `$procmux$1949_CMP0' from module `\usb_tx_phy'.

            
              Cell `$procmux$1953_CMP0' is identical to cell `$procmux$1601_CMP0'.

            
                Redirecting output \Y: $procmux$1953_CMP = $procmux$1601_CMP

            
                Removing $eq cell `$procmux$1953_CMP0' from module `\usb_tx_phy'.

            
              Cell `$procmux$1961_CMP0' is identical to cell `$procmux$1675_CMP0'.

            
                Redirecting output \Y: $procmux$1961_CMP = $procmux$1675_CMP

            
                Removing $eq cell `$procmux$1961_CMP0' from module `\usb_tx_phy'.

            
              Cell `$procmux$1965_CMP0' is identical to cell `$procmux$1679_CMP0'.

            
                Redirecting output \Y: $procmux$1965_CMP = $procmux$1679_CMP

            
                Removing $eq cell `$procmux$1965_CMP0' from module `\usb_tx_phy'.

            
              Cell `$procmux$1971_CMP0' is identical to cell `$procmux$1593_CMP0'.

            
                Redirecting output \Y: $procmux$1971_CMP = $procmux$1593_CMP

            
                Removing $eq cell `$procmux$1971_CMP0' from module `\usb_tx_phy'.

            
              Cell `$procmux$1975_CMP0' is identical to cell `$procmux$1597_CMP0'.

            
                Redirecting output \Y: $procmux$1975_CMP = $procmux$1597_CMP

            
                Removing $eq cell `$procmux$1975_CMP0' from module `\usb_tx_phy'.

            
              Cell `$procmux$1979_CMP0' is identical to cell `$procmux$1601_CMP0'.

            
                Redirecting output \Y: $procmux$1979_CMP = $procmux$1601_CMP

            
                Removing $eq cell `$procmux$1979_CMP0' from module `\usb_tx_phy'.

            
            Removed a total of 209 cells.


            7.4. Executing OPT_MUXTREE pass (detect dead branches in mux trees).

            
            Running muxtree optimizier on module \usb_phy..

            
              Creating internal representation of mux trees.

            
              Evaluating internal representation of mux trees.

            
              Analyzing evaluation results.

            
            Running muxtree optimizier on module \usb_rx_phy..

            
              Creating internal representation of mux trees.

            
              Evaluating internal representation of mux trees.

            
              Analyzing evaluation results.

            
                dead port 2/2 on $mux $procmux$1004.

            
                dead port 2/7 on $pmux $procmux$1018.

            
                dead port 3/7 on $pmux $procmux$1018.

            
                dead port 4/7 on $pmux $procmux$1018.

            
                dead port 5/7 on $pmux $procmux$1018.

            
                dead port 6/7 on $pmux $procmux$1018.

            
                dead port 7/7 on $pmux $procmux$1018.

            
                dead port 2/2 on $mux $procmux$1040.

            
                dead port 1/2 on $mux $procmux$1053.

            
                dead port 2/7 on $pmux $procmux$1055.

            
                dead port 3/7 on $pmux $procmux$1055.

            
                dead port 4/7 on $pmux $procmux$1055.

            
                dead port 5/7 on $pmux $procmux$1055.

            
                dead port 6/7 on $pmux $procmux$1055.

            
                dead port 7/7 on $pmux $procmux$1055.

            
                dead port 2/2 on $mux $procmux$1077.

            
                dead port 1/2 on $mux $procmux$1089.

            
                dead port 2/7 on $pmux $procmux$1091.

            
                dead port 3/7 on $pmux $procmux$1091.

            
                dead port 4/7 on $pmux $procmux$1091.

            
                dead port 5/7 on $pmux $procmux$1091.

            
                dead port 6/7 on $pmux $procmux$1091.

            
                dead port 7/7 on $pmux $procmux$1091.

            
                dead port 2/2 on $mux $procmux$1113.

            
                dead port 1/2 on $mux $procmux$1126.

            
                dead port 2/7 on $pmux $procmux$1128.

            
                dead port 3/7 on $pmux $procmux$1128.

            
                dead port 4/7 on $pmux $procmux$1128.

            
                dead port 5/7 on $pmux $procmux$1128.

            
                dead port 6/7 on $pmux $procmux$1128.

            
                dead port 7/7 on $pmux $procmux$1128.

            
                dead port 2/2 on $mux $procmux$1150.

            
                dead port 2/8 on $pmux $procmux$1159.

            
                dead port 3/8 on $pmux $procmux$1159.

            
                dead port 4/8 on $pmux $procmux$1159.

            
                dead port 5/8 on $pmux $procmux$1159.

            
                dead port 6/8 on $pmux $procmux$1159.

            
                dead port 7/8 on $pmux $procmux$1159.

            
                dead port 8/8 on $pmux $procmux$1159.

            
                dead port 2/2 on $mux $procmux$1187.

            
                dead port 2/8 on $pmux $procmux$1196.

            
                dead port 3/8 on $pmux $procmux$1196.

            
                dead port 4/8 on $pmux $procmux$1196.

            
                dead port 5/8 on $pmux $procmux$1196.

            
                dead port 6/8 on $pmux $procmux$1196.

            
                dead port 7/8 on $pmux $procmux$1196.

            
                dead port 8/8 on $pmux $procmux$1196.

            
                dead port 2/2 on $mux $procmux$1224.

            
                dead port 1/8 on $pmux $procmux$1233.

            
                dead port 2/8 on $pmux $procmux$1233.

            
                dead port 3/8 on $pmux $procmux$1233.

            
                dead port 4/8 on $pmux $procmux$1233.

            
                dead port 5/8 on $pmux $procmux$1233.

            
                dead port 6/8 on $pmux $procmux$1233.

            
                dead port 7/8 on $pmux $procmux$1233.

            
                dead port 2/2 on $mux $procmux$1261.

            
                dead port 2/2 on $mux $procmux$305.

            
                dead port 2/3 on $pmux $procmux$316.

            
                dead port 3/3 on $pmux $procmux$316.

            
                dead port 2/4 on $pmux $procmux$328.

            
                dead port 3/4 on $pmux $procmux$328.

            
                dead port 4/4 on $pmux $procmux$328.

            
                dead port 1/4 on $pmux $procmux$343.

            
                dead port 2/4 on $pmux $procmux$343.

            
                dead port 3/4 on $pmux $procmux$343.

            
                dead port 2/2 on $mux $procmux$561.

            
                dead port 2/2 on $mux $procmux$597.

            
                dead port 2/2 on $mux $procmux$633.

            
                dead port 2/2 on $mux $procmux$662.

            
                dead port 2/2 on $mux $procmux$664.

            
                dead port 2/3 on $pmux $procmux$690.

            
                dead port 3/3 on $pmux $procmux$690.

            
                dead port 2/2 on $mux $procmux$696.

            
                dead port 2/3 on $pmux $procmux$722.

            
                dead port 3/3 on $pmux $procmux$722.

            
                dead port 2/2 on $mux $procmux$728.

            
                dead port 2/4 on $pmux $procmux$751.

            
                dead port 3/4 on $pmux $procmux$751.

            
                dead port 4/4 on $pmux $procmux$751.

            
                dead port 2/2 on $mux $procmux$761.

            
                dead port 2/4 on $pmux $procmux$784.

            
                dead port 3/4 on $pmux $procmux$784.

            
                dead port 4/4 on $pmux $procmux$784.

            
                dead port 2/2 on $mux $procmux$794.

            
                dead port 2/5 on $pmux $procmux$814.

            
                dead port 3/5 on $pmux $procmux$814.

            
                dead port 4/5 on $pmux $procmux$814.

            
                dead port 5/5 on $pmux $procmux$814.

            
                dead port 2/2 on $mux $procmux$828.

            
                dead port 2/5 on $pmux $procmux$848.

            
                dead port 3/5 on $pmux $procmux$848.

            
                dead port 4/5 on $pmux $procmux$848.

            
                dead port 5/5 on $pmux $procmux$848.

            
                dead port 2/2 on $mux $procmux$862.

            
                dead port 2/6 on $pmux $procmux$879.

            
                dead port 3/6 on $pmux $procmux$879.

            
                dead port 4/6 on $pmux $procmux$879.

            
                dead port 5/6 on $pmux $procmux$879.

            
                dead port 6/6 on $pmux $procmux$879.

            
                dead port 2/2 on $mux $procmux$897.

            
                dead port 2/6 on $pmux $procmux$914.

            
                dead port 3/6 on $pmux $procmux$914.

            
                dead port 4/6 on $pmux $procmux$914.

            
                dead port 5/6 on $pmux $procmux$914.

            
                dead port 6/6 on $pmux $procmux$914.

            
                dead port 2/2 on $mux $procmux$932.

            
                dead port 2/7 on $pmux $procmux$946.

            
                dead port 3/7 on $pmux $procmux$946.

            
                dead port 4/7 on $pmux $procmux$946.

            
                dead port 5/7 on $pmux $procmux$946.

            
                dead port 6/7 on $pmux $procmux$946.

            
                dead port 7/7 on $pmux $procmux$946.

            
                dead port 2/2 on $mux $procmux$968.

            
                dead port 2/7 on $pmux $procmux$982.

            
                dead port 3/7 on $pmux $procmux$982.

            
                dead port 4/7 on $pmux $procmux$982.

            
                dead port 5/7 on $pmux $procmux$982.

            
                dead port 6/7 on $pmux $procmux$982.

            
                dead port 7/7 on $pmux $procmux$982.

            
            Running muxtree optimizier on module \usb_tx_phy..

            
              Creating internal representation of mux trees.

            
              Evaluating internal representation of mux trees.

            
              Analyzing evaluation results.

            
                dead port 2/2 on $mux $procmux$1714.

            
                dead port 2/2 on $mux $procmux$1736.

            
                dead port 2/3 on $pmux $procmux$1755.

            
                dead port 3/3 on $pmux $procmux$1755.

            
                dead port 2/3 on $pmux $procmux$1778.

            
                dead port 3/3 on $pmux $procmux$1778.

            
                dead port 2/3 on $pmux $procmux$1801.

            
                dead port 3/3 on $pmux $procmux$1801.

            
                dead port 2/4 on $pmux $procmux$1821.

            
                dead port 3/4 on $pmux $procmux$1821.

            
                dead port 4/4 on $pmux $procmux$1821.

            
                dead port 2/4 on $pmux $procmux$1845.

            
                dead port 3/4 on $pmux $procmux$1845.

            
                dead port 4/4 on $pmux $procmux$1845.

            
                dead port 2/4 on $pmux $procmux$1869.

            
                dead port 3/4 on $pmux $procmux$1869.

            
                dead port 4/4 on $pmux $procmux$1869.

            
                dead port 2/4 on $pmux $procmux$1893.

            
                dead port 3/4 on $pmux $procmux$1893.

            
                dead port 4/4 on $pmux $procmux$1893.

            
                dead port 2/5 on $pmux $procmux$1912.

            
                dead port 3/5 on $pmux $procmux$1912.

            
                dead port 4/5 on $pmux $procmux$1912.

            
                dead port 5/5 on $pmux $procmux$1912.

            
                dead port 2/6 on $pmux $procmux$1934.

            
                dead port 3/6 on $pmux $procmux$1934.

            
                dead port 4/6 on $pmux $procmux$1934.

            
                dead port 5/6 on $pmux $procmux$1934.

            
                dead port 6/6 on $pmux $procmux$1934.

            
                dead port 1/6 on $pmux $procmux$1960.

            
                dead port 2/6 on $pmux $procmux$1960.

            
                dead port 3/6 on $pmux $procmux$1960.

            
                dead port 4/6 on $pmux $procmux$1960.

            
                dead port 5/6 on $pmux $procmux$1960.

            
            Removed 153 multiplexer ports.


            7.5. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).

            
              Optimizing cells in module \usb_phy.

            
              Optimizing cells in module \usb_rx_phy.

            
                New ctrl vector for $pmux cell $procmux$272: $procmux$273_CMP

            
                New ctrl vector for $pmux cell $procmux$533: { $procmux$1035_CMP $procmux$1031_CMP $procmux$1027_CMP $procmux$1023_CMP $procmux$1019_CMP $procmux$1160_CMP }

            
                New ctrl vector for $pmux cell $procmux$569: { $procmux$1019_CMP $auto$opt_reduce.cc:123:opt_mux$2040 }

            
              Optimizing cells in module \usb_tx_phy.

            
                New ctrl vector for $pmux cell $procmux$1592: { $procmux$1597_CMP $procmux$1593_CMP }

            
                New ctrl vector for $pmux cell $procmux$1615: $procmux$1593_CMP

            
                New ctrl vector for $pmux cell $procmux$1638: { $procmux$1597_CMP $procmux$1593_CMP }

            
            Performed a total of 6 changes.


            7.6. Executing OPT_SHARE pass (detect identical cells).

            
            Finding identical cells in module `\usb_phy'.

            
            Finding identical cells in module `\usb_rx_phy'.

            
              Cell `$procmux$1157' is identical to cell `$procmux$1050'.

            
                Redirecting output \Y: $procmux$1157_Y = $procmux$1050_Y

            
                Removing $mux cell `$procmux$1157' from module `\usb_rx_phy'.

            
              Cell `$procmux$749' is identical to cell `$procmux$1050'.

            
                Redirecting output \Y: $procmux$749_Y = $procmux$1050_Y

            
                Removing $mux cell `$procmux$749' from module `\usb_rx_phy'.

            
              Cell `$procmux$812' is identical to cell `$procmux$688'.

            
                Redirecting output \Y: $procmux$812_Y = $procmux$688_Y

            
                Removing $mux cell `$procmux$812' from module `\usb_rx_phy'.

            
              Cell `$procmux$877' is identical to cell `$procmux$1050'.

            
                Redirecting output \Y: $procmux$877_Y = $procmux$1050_Y

            
                Removing $mux cell `$procmux$877' from module `\usb_rx_phy'.

            
            Finding identical cells in module `\usb_tx_phy'.

            
              Cell `$procmux$1776' is identical to cell `$procmux$1753'.

            
                Redirecting output \Y: $procmux$1776_Y = $procmux$1753_Y

            
                Removing $mux cell `$procmux$1776' from module `\usb_tx_phy'.

            
              Cell `$procmux$1891' is identical to cell `$procmux$1867'.

            
                Redirecting output \Y: $procmux$1891_Y = $procmux$1867_Y

            
                Removing $mux cell `$procmux$1891' from module `\usb_tx_phy'.

            
              Cell `$procmux$1638' is identical to cell `$procmux$1592'.

            
                Redirecting output \Y: $procmux$1638_Y = $procmux$1592_Y

            
                Removing $pmux cell `$procmux$1638' from module `\usb_tx_phy'.

            
            Removed a total of 7 cells.


            7.7. Executing OPT_RMDFF pass (remove dff with constant values).

            
            Replaced 0 DFF cells.


            7.8. Executing OPT_RMUNUSED pass (remove unused cells and wires).

            
            Finding unused cells or wires in module \usb_phy..

            
              removed 5 unused temporary wires.

            
            Finding unused cells or wires in module \usb_rx_phy..

            
              removed 341 unused temporary wires.

            
            Finding unused cells or wires in module \usb_tx_phy..

            
              removed 196 unused temporary wires.


            7.9. Executing OPT_CONST pass (perform const folding).


            7.10. Rerunning OPT passes. (Maybe there is more to do..)


            7.11. Executing OPT_MUXTREE pass (detect dead branches in mux trees).

            
            Running muxtree optimizier on module \usb_phy..

            
              Creating internal representation of mux trees.

            
              Evaluating internal representation of mux trees.

            
              Analyzing evaluation results.

            
            Running muxtree optimizier on module \usb_rx_phy..

            
              Creating internal representation of mux trees.

            
              Evaluating internal representation of mux trees.

            
              Analyzing evaluation results.

            
            Running muxtree optimizier on module \usb_tx_phy..

            
              Creating internal representation of mux trees.

            
              Evaluating internal representation of mux trees.

            
              Analyzing evaluation results.

            
            Removed 0 multiplexer ports.


            7.12. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).

            
              Optimizing cells in module \usb_phy.

            
              Optimizing cells in module \usb_rx_phy.

            
                New ctrl vector for $pmux cell $procmux$533: { $auto$opt_reduce.cc:123:opt_mux$2044 $procmux$1019_CMP $auto$opt_reduce.cc:123:opt_mux$2042 }

            
              Optimizing cells in module \usb_tx_phy.

            
            Performed a total of 1 changes.


            7.13. Executing OPT_SHARE pass (detect identical cells).

            
            Finding identical cells in module `\usb_phy'.

            
            Finding identical cells in module `\usb_rx_phy'.

            
            Finding identical cells in module `\usb_tx_phy'.

            
            Removed a total of 0 cells.


            7.14. Executing OPT_RMDFF pass (remove dff with constant values).

            
            Replaced 0 DFF cells.


            7.15. Executing OPT_RMUNUSED pass (remove unused cells and wires).

            
            Finding unused cells or wires in module \usb_phy..

            
            Finding unused cells or wires in module \usb_rx_phy..

            
            Finding unused cells or wires in module \usb_tx_phy..


            7.16. Executing OPT_CONST pass (perform const folding).


            7.17. Rerunning OPT passes. (Maybe there is more to do..)


            7.18. Executing OPT_MUXTREE pass (detect dead branches in mux trees).

            
            Running muxtree optimizier on module \usb_phy..

            
              Creating internal representation of mux trees.

            
              Evaluating internal representation of mux trees.

            
              Analyzing evaluation results.

            
            Running muxtree optimizier on module \usb_rx_phy..

            
              Creating internal representation of mux trees.

            
              Evaluating internal representation of mux trees.

            
              Analyzing evaluation results.

            
            Running muxtree optimizier on module \usb_tx_phy..

            
              Creating internal representation of mux trees.

            
              Evaluating internal representation of mux trees.

            
              Analyzing evaluation results.

            
            Removed 0 multiplexer ports.


            7.19. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).

            
              Optimizing cells in module \usb_phy.

            
              Optimizing cells in module \usb_rx_phy.

            
              Optimizing cells in module \usb_tx_phy.

            
            Performed a total of 0 changes.


            7.20. Executing OPT_SHARE pass (detect identical cells).

            
            Finding identical cells in module `\usb_phy'.

            
            Finding identical cells in module `\usb_rx_phy'.

            
            Finding identical cells in module `\usb_tx_phy'.

            
            Removed a total of 0 cells.


            7.21. Executing OPT_RMDFF pass (remove dff with constant values).

            
            Replaced 0 DFF cells.


            7.22. Executing OPT_RMUNUSED pass (remove unused cells and wires).

            
            Finding unused cells or wires in module \usb_phy..

            
            Finding unused cells or wires in module \usb_rx_phy..

            
            Finding unused cells or wires in module \usb_tx_phy..


            7.23. Executing OPT_CONST pass (perform const folding).


            7.24. Optimizing in-memory representation of design.


            7.25. Finished OPT passes. (There is nothing left to do.)


            8. Executing MEMORY pass.


            8.1. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).


            8.2. Executing MEMORY_COLLECT pass (generating $mem cells).


            8.3. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).


            9. Executing OPT pass (performing simple optimizations).


            9.1. Optimizing in-memory representation of design.


            9.2. Executing OPT_CONST pass (perform const folding).


            9.3. Executing OPT_SHARE pass (detect identical cells).

            
            Full command line: opt_share -nomux

            
            Finding identical cells in module `\usb_phy'.

            
            Finding identical cells in module `\usb_rx_phy'.

            
            Finding identical cells in module `\usb_tx_phy'.

            
            Removed a total of 0 cells.


            9.4. Executing OPT_MUXTREE pass (detect dead branches in mux trees).

            
            Running muxtree optimizier on module \usb_phy..

            
              Creating internal representation of mux trees.

            
              Evaluating internal representation of mux trees.

            
              Analyzing evaluation results.

            
            Running muxtree optimizier on module \usb_rx_phy..

            
              Creating internal representation of mux trees.

            
              Evaluating internal representation of mux trees.

            
              Analyzing evaluation results.

            
            Running muxtree optimizier on module \usb_tx_phy..

            
              Creating internal representation of mux trees.

            
              Evaluating internal representation of mux trees.

            
              Analyzing evaluation results.

            
            Removed 0 multiplexer ports.


            9.5. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).

            
              Optimizing cells in module \usb_phy.

            
              Optimizing cells in module \usb_rx_phy.

            
              Optimizing cells in module \usb_tx_phy.

            
            Performed a total of 0 changes.


            9.6. Executing OPT_SHARE pass (detect identical cells).

            
            Finding identical cells in module `\usb_phy'.

            
            Finding identical cells in module `\usb_rx_phy'.

            
            Finding identical cells in module `\usb_tx_phy'.

            
            Removed a total of 0 cells.


            9.7. Executing OPT_RMDFF pass (remove dff with constant values).

            
            Replaced 0 DFF cells.


            9.8. Executing OPT_RMUNUSED pass (remove unused cells and wires).

            
            Finding unused cells or wires in module \usb_phy..

            
            Finding unused cells or wires in module \usb_rx_phy..

            
            Finding unused cells or wires in module \usb_tx_phy..


            9.9. Executing OPT_CONST pass (perform const folding).


            9.10. Optimizing in-memory representation of design.


            9.11. Finished OPT passes. (There is nothing left to do.)


            10. Executing TECHMAP pass (map to technology primitives).


            10.1. Executing Verilog-2005 frontend.

            
            Full command line: read_verilog <stdcells.v>

            
            Parsing Verilog input from `<stdcells.v>' to AST representation.

            
            Generating RTLIL representation for module `\$not'.

            
            Generating RTLIL representation for module `\$pos'.

            
            Generating RTLIL representation for module `\$neg'.

            
            Generating RTLIL representation for module `\$and'.

            
            Generating RTLIL representation for module `\$or'.

            
            Generating RTLIL representation for module `\$xor'.

            
            Generating RTLIL representation for module `\$xnor'.

            
            Generating RTLIL representation for module `\$reduce_and'.

            
            Generating RTLIL representation for module `\$reduce_or'.

            
            Generating RTLIL representation for module `\$reduce_xor'.

            
            Generating RTLIL representation for module `\$reduce_xnor'.

            
            Generating RTLIL representation for module `\$reduce_bool'.

            
            Generating RTLIL representation for module `\$shift'.

            
            Generating RTLIL representation for module `\$shl'.

            
            Generating RTLIL representation for module `\$shr'.

            
            Generating RTLIL representation for module `\$sshl'.

            
            Generating RTLIL representation for module `\$sshr'.

            
            Generating RTLIL representation for module `\$fulladd'.

            
            Generating RTLIL representation for module `\$alu'.

            
            Generating RTLIL representation for module `\$lt'.

            
            Generating RTLIL representation for module `\$le'.

            
            Generating RTLIL representation for module `\$eq'.

            
            Generating RTLIL representation for module `\$ne'.

            
            Generating RTLIL representation for module `\$ge'.

            
            Generating RTLIL representation for module `\$gt'.

            
            Generating RTLIL representation for module `\$add'.

            
            Generating RTLIL representation for module `\$sub'.

            
            Generating RTLIL representation for module `\$logic_not'.

            
            Generating RTLIL representation for module `\$logic_and'.

            
            Generating RTLIL representation for module `\$logic_or'.

            
            Generating RTLIL representation for module `\$mux'.

            
            Generating RTLIL representation for module `\$pmux'.

            
            Generating RTLIL representation for module `\$safe_pmux'.

            
            Generating RTLIL representation for module `\$dff'.

            
            Generating RTLIL representation for module `\$adff'.

            
            Successfully finished Verilog frontend.


            10.2. Executing AST frontend in derive mode using pre-parsed AST for module `$add'.

            
            Parameter \A_SIGNED = 0

            
            Parameter \B_SIGNED = 0

            
            Parameter \A_WIDTH = 5

            
            Parameter \B_WIDTH = 5

            
            Parameter \Y_WIDTH = 5

            
            Generating RTLIL representation for module `$paramod$add\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=5\Y_WIDTH=5'.


            10.3. Continuing TECHMAP pass.

            
            Mapping `usb_phy.$add$rtl/usb_phy.v:178$6' using `$paramod$add\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=5\Y_WIDTH=5'.


            10.4. Executing AST frontend in derive mode using pre-parsed AST for module `$eq'.

            
            Parameter \A_SIGNED = 0

            
            Parameter \B_SIGNED = 0

            
            Parameter \A_WIDTH = 5

            
            Parameter \B_WIDTH = 5

            
            Parameter \Y_WIDTH = 1

            
            Generating RTLIL representation for module `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=5\Y_WIDTH=1'.


            10.5. Continuing TECHMAP pass.

            
            Mapping `usb_phy.$eq$rtl/usb_phy.v:181$8' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=5\Y_WIDTH=1'.


            10.6. Executing AST frontend in derive mode using pre-parsed AST for module `$logic_and'.

            
            Parameter \A_SIGNED = 0

            
            Parameter \B_SIGNED = 0

            
            Parameter \A_WIDTH = 1

            
            Parameter \B_WIDTH = 1

            
            Parameter \Y_WIDTH = 1

            
            Generating RTLIL representation for module `$paramod$logic_and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.


            10.7. Continuing TECHMAP pass.

            
            Mapping `usb_phy.$logic_and$rtl/usb_phy.v:178$5' using `$paramod$logic_and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.


            10.8. Executing AST frontend in derive mode using pre-parsed AST for module `$logic_not'.

            
            Parameter \A_SIGNED = 0

            
            Parameter \A_WIDTH = 1

            
            Parameter \Y_WIDTH = 1

            
            Generating RTLIL representation for module `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.


            10.9. Continuing TECHMAP pass.

            
            Mapping `usb_phy.$logic_not$rtl/usb_phy.v:174$2' using `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_phy.$logic_not$rtl/usb_phy.v:178$4' using `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.


            10.10. Executing AST frontend in derive mode using pre-parsed AST for module `$ne'.

            
            Parameter \A_SIGNED = 0

            
            Parameter \B_SIGNED = 0

            
            Parameter \A_WIDTH = 2

            
            Parameter \B_WIDTH = 2

            
            Parameter \Y_WIDTH = 1

            
            Generating RTLIL representation for module `$paramod$ne\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=1'.


            10.11. Continuing TECHMAP pass.

            
            Mapping `usb_phy.$ne$rtl/usb_phy.v:176$3' using `$paramod$ne\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=1'.


            10.12. Executing AST frontend in derive mode using pre-parsed AST for module `$dff'.

            
            Parameter \WIDTH = 5

            
            Parameter \CLK_POLARITY = 1'1

            
            Generating RTLIL representation for module `$paramod$dff\WIDTH=5\CLK_POLARITY=1'1'.


            10.13. Continuing TECHMAP pass.

            
            Mapping `usb_phy.$procdff$1980' using `$paramod$dff\WIDTH=5\CLK_POLARITY=1'1'.


            10.14. Executing AST frontend in derive mode using pre-parsed AST for module `$dff'.

            
            Parameter \WIDTH = 1

            
            Parameter \CLK_POLARITY = 1'1

            
            Generating RTLIL representation for module `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.


            10.15. Continuing TECHMAP pass.

            
            Mapping `usb_phy.$procdff$1981' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.


            10.16. Executing AST frontend in derive mode using pre-parsed AST for module `$mux'.

            
            Parameter \WIDTH = 5

            
            Generating RTLIL representation for module `$paramod$mux\WIDTH=5'.


            10.17. Continuing TECHMAP pass.

            
            Mapping `usb_phy.$procmux$220' using `$paramod$mux\WIDTH=5'.

            
            Mapping `usb_phy.$procmux$223' using `$paramod$mux\WIDTH=5'.

            
            Mapping `usb_phy.$procmux$226' using `$paramod$mux\WIDTH=5'.


            10.18. Executing AST frontend in derive mode using pre-parsed AST for module `$add'.

            
            Parameter \A_SIGNED = 0

            
            Parameter \B_SIGNED = 0

            
            Parameter \A_WIDTH = 3

            
            Parameter \B_WIDTH = 3

            
            Parameter \Y_WIDTH = 3

            
            Generating RTLIL representation for module `$paramod$add\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'.


            10.19. Continuing TECHMAP pass.

            
            Mapping `usb_rx_phy.$add$rtl/usb_rx_phy.v:399$90' using `$paramod$add\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$add$rtl/usb_rx_phy.v:432$109' using `$paramod$add\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'.


            10.20. Executing AST frontend in derive mode using pre-parsed AST for module `$and'.

            
            Parameter \A_SIGNED = 0

            
            Parameter \B_SIGNED = 0

            
            Parameter \A_WIDTH = 1

            
            Parameter \B_WIDTH = 1

            
            Parameter \Y_WIDTH = 1

            
            Generating RTLIL representation for module `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.


            10.21. Continuing TECHMAP pass.

            
            Mapping `usb_rx_phy.$and$rtl/usb_rx_phy.v:145$14' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$and$rtl/usb_rx_phy.v:166$25' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$and$rtl/usb_rx_phy.v:171$32' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$and$rtl/usb_rx_phy.v:174$37' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$and$rtl/usb_rx_phy.v:175$39' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$and$rtl/usb_rx_phy.v:176$42' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$and$rtl/usb_rx_phy.v:404$93' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$and$rtl/usb_rx_phy.v:404$94' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$and$rtl/usb_rx_phy.v:404$96' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$and$rtl/usb_rx_phy.v:404$97' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$and$rtl/usb_rx_phy.v:445$121' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$and$rtl/usb_rx_phy.v:445$122' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$and$rtl/usb_rx_phy.v:449$126' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$and$rtl/usb_rx_phy.v:449$128' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$and$rtl/usb_rx_phy.v:449$129' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.


            10.22. Executing AST frontend in derive mode using pre-parsed AST for module `$reduce_or'.

            
            Parameter \A_WIDTH = 6

            
            Parameter \Y_WIDTH = 1

            
            Generating RTLIL representation for module `$paramod$reduce_or\A_WIDTH=6\Y_WIDTH=1'.


            10.23. Continuing TECHMAP pass.

            
            Mapping `usb_rx_phy.$auto$opt_reduce.cc:127:opt_mux$2041' using `$paramod$reduce_or\A_WIDTH=6\Y_WIDTH=1'.


            10.24. Executing AST frontend in derive mode using pre-parsed AST for module `$reduce_or'.

            
            Parameter \A_WIDTH = 3

            
            Parameter \Y_WIDTH = 1

            
            Generating RTLIL representation for module `$paramod$reduce_or\A_WIDTH=3\Y_WIDTH=1'.


            10.25. Continuing TECHMAP pass.

            
            Mapping `usb_rx_phy.$auto$opt_reduce.cc:127:opt_mux$2043' using `$paramod$reduce_or\A_WIDTH=3\Y_WIDTH=1'.


            10.26. Executing AST frontend in derive mode using pre-parsed AST for module `$reduce_or'.

            
            Parameter \A_WIDTH = 2

            
            Parameter \Y_WIDTH = 1

            
            Generating RTLIL representation for module `$paramod$reduce_or\A_WIDTH=2\Y_WIDTH=1'.


            10.27. Continuing TECHMAP pass.

            
            Mapping `usb_rx_phy.$auto$opt_reduce.cc:127:opt_mux$2045' using `$paramod$reduce_or\A_WIDTH=2\Y_WIDTH=1'.


            10.28. Executing AST frontend in derive mode using pre-parsed AST for module `$eq'.

            
            Parameter \A_SIGNED = 0

            
            Parameter \B_SIGNED = 0

            
            Parameter \A_WIDTH = 3

            
            Parameter \B_WIDTH = 3

            
            Parameter \Y_WIDTH = 1

            
            Generating RTLIL representation for module `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=1'.


            10.29. Continuing TECHMAP pass.

            
            Mapping `usb_rx_phy.$eq$rtl/usb_rx_phy.v:402$91' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$eq$rtl/usb_rx_phy.v:441$114' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:160$18' using `$paramod$logic_and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:162$21' using `$paramod$logic_and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:216$49' using `$paramod$logic_and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:268$60' using `$paramod$logic_and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:268$62' using `$paramod$logic_and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:268$64' using `$paramod$logic_and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:272$65' using `$paramod$logic_and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:276$66' using `$paramod$logic_and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:354$75' using `$paramod$logic_and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:356$76' using `$paramod$logic_and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:380$82' using `$paramod$logic_and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:415$101' using `$paramod$logic_and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:415$103' using `$paramod$logic_and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:432$108' using `$paramod$logic_and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:441$115' using `$paramod$logic_and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:443$116' using `$paramod$logic_and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:443$118' using `$paramod$logic_and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_not$rtl/usb_rx_phy.v:145$13' using `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_not$rtl/usb_rx_phy.v:162$19' using `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_not$rtl/usb_rx_phy.v:162$20' using `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_not$rtl/usb_rx_phy.v:174$36' using `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_not$rtl/usb_rx_phy.v:175$38' using `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_not$rtl/usb_rx_phy.v:208$47' using `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_not$rtl/usb_rx_phy.v:268$61' using `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_not$rtl/usb_rx_phy.v:268$63' using `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_not$rtl/usb_rx_phy.v:380$84' using `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_not$rtl/usb_rx_phy.v:394$87' using `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_not$rtl/usb_rx_phy.v:398$88' using `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_not$rtl/usb_rx_phy.v:415$102' using `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_not$rtl/usb_rx_phy.v:449$125' using `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.


            10.30. Executing AST frontend in derive mode using pre-parsed AST for module `$logic_or'.

            
            Parameter \A_SIGNED = 0

            
            Parameter \B_SIGNED = 0

            
            Parameter \A_WIDTH = 1

            
            Parameter \B_WIDTH = 1

            
            Parameter \Y_WIDTH = 1

            
            Generating RTLIL representation for module `$paramod$logic_or\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.


            10.31. Continuing TECHMAP pass.

            
            Mapping `usb_rx_phy.$logic_or$rtl/usb_rx_phy.v:398$89' using `$paramod$logic_or\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.


            10.32. Executing AST frontend in derive mode using pre-parsed AST for module `$ne'.

            
            Parameter \A_SIGNED = 0

            
            Parameter \B_SIGNED = 0

            
            Parameter \A_WIDTH = 1

            
            Parameter \B_WIDTH = 1

            
            Parameter \Y_WIDTH = 1

            
            Generating RTLIL representation for module `$paramod$ne\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.


            10.33. Continuing TECHMAP pass.

            
            Mapping `usb_rx_phy.$ne$rtl/usb_rx_phy.v:200$45' using `$paramod$ne\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.


            10.34. Executing AST frontend in derive mode using pre-parsed AST for module `$or'.

            
            Parameter \A_SIGNED = 0

            
            Parameter \B_SIGNED = 0

            
            Parameter \A_WIDTH = 1

            
            Parameter \B_WIDTH = 1

            
            Parameter \Y_WIDTH = 1

            
            Generating RTLIL representation for module `$paramod$or\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.


            10.35. Continuing TECHMAP pass.

            
            Mapping `usb_rx_phy.$or$rtl/usb_rx_phy.v:140$10' using `$paramod$or\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$or$rtl/usb_rx_phy.v:140$9' using `$paramod$or\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$or$rtl/usb_rx_phy.v:167$28' using `$paramod$or\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$or$rtl/usb_rx_phy.v:172$35' using `$paramod$or\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$or$rtl/usb_rx_phy.v:412$99' using `$paramod$or\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$procdff$1982' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.

            
            Mapping `usb_rx_phy.$procdff$1983' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.

            
            Mapping `usb_rx_phy.$procdff$1984' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.

            
            Mapping `usb_rx_phy.$procdff$1985' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.

            
            Mapping `usb_rx_phy.$procdff$1986' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.

            
            Mapping `usb_rx_phy.$procdff$1987' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.

            
            Mapping `usb_rx_phy.$procdff$1988' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.

            
            Mapping `usb_rx_phy.$procdff$1989' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.

            
            Mapping `usb_rx_phy.$procdff$1990' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.

            
            Mapping `usb_rx_phy.$procdff$1991' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.

            
            Mapping `usb_rx_phy.$procdff$1992' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.

            
            Mapping `usb_rx_phy.$procdff$1993' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.

            
            Mapping `usb_rx_phy.$procdff$1994' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.

            
            Mapping `usb_rx_phy.$procdff$1995' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.

            
            Mapping `usb_rx_phy.$procdff$1996' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.


            10.36. Executing AST frontend in derive mode using pre-parsed AST for module `$dff'.

            
            Parameter \WIDTH = 2

            
            Parameter \CLK_POLARITY = 1'1

            
            Generating RTLIL representation for module `$paramod$dff\WIDTH=2\CLK_POLARITY=1'1'.


            10.37. Continuing TECHMAP pass.

            
            Mapping `usb_rx_phy.$procdff$1997' using `$paramod$dff\WIDTH=2\CLK_POLARITY=1'1'.

            
            Mapping `usb_rx_phy.$procdff$1998' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.

            
            Mapping `usb_rx_phy.$procdff$1999' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.

            
            Mapping `usb_rx_phy.$procdff$2000' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.


            10.38. Executing AST frontend in derive mode using pre-parsed AST for module `$dff'.

            
            Parameter \WIDTH = 3

            
            Parameter \CLK_POLARITY = 1'1

            
            Generating RTLIL representation for module `$paramod$dff\WIDTH=3\CLK_POLARITY=1'1'.


            10.39. Continuing TECHMAP pass.

            
            Mapping `usb_rx_phy.$procdff$2001' using `$paramod$dff\WIDTH=3\CLK_POLARITY=1'1'.

            
            Mapping `usb_rx_phy.$procdff$2002' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.

            
            Mapping `usb_rx_phy.$procdff$2003' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.

            
            Mapping `usb_rx_phy.$procdff$2004' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.

            
            Mapping `usb_rx_phy.$procdff$2005' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.

            
            Mapping `usb_rx_phy.$procdff$2006' using `$paramod$dff\WIDTH=3\CLK_POLARITY=1'1'.

            
            Mapping `usb_rx_phy.$procdff$2007' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.

            
            Mapping `usb_rx_phy.$procdff$2008' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.


            10.40. Executing AST frontend in derive mode using pre-parsed AST for module `$dff'.

            
            Parameter \WIDTH = 8

            
            Parameter \CLK_POLARITY = 1'1

            
            Generating RTLIL representation for module `$paramod$dff\WIDTH=8\CLK_POLARITY=1'1'.


            10.41. Continuing TECHMAP pass.

            
            Mapping `usb_rx_phy.$procdff$2009' using `$paramod$dff\WIDTH=8\CLK_POLARITY=1'1'.

            
            Mapping `usb_rx_phy.$procdff$2010' using `$paramod$dff\WIDTH=3\CLK_POLARITY=1'1'.

            
            Mapping `usb_rx_phy.$procdff$2011' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.

            
            Mapping `usb_rx_phy.$procdff$2012' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.

            
            Mapping `usb_rx_phy.$procdff$2013' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.

            
            Mapping `usb_rx_phy.$procdff$2014' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.

            
            Mapping `usb_rx_phy.$procmux$1003_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=1'.


            10.42. Executing AST frontend in derive mode using pre-parsed AST for module `$mux'.

            
            Parameter \WIDTH = 3

            
            Generating RTLIL representation for module `$paramod$mux\WIDTH=3'.


            10.43. Continuing TECHMAP pass.

            
            Mapping `usb_rx_phy.$procmux$1016' using `$paramod$mux\WIDTH=3'.

            
            Mapping `usb_rx_phy.$procmux$1019_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$procmux$1023_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$procmux$1027_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$procmux$1031_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$procmux$1035_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=1'.


            10.44. Executing AST frontend in derive mode using pre-parsed AST for module `$mux'.

            
            Parameter \WIDTH = 1

            
            Generating RTLIL representation for module `$paramod$mux\WIDTH=1'.


            10.45. Continuing TECHMAP pass.

            
            Mapping `usb_rx_phy.$procmux$1050' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_rx_phy.$procmux$1123' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_rx_phy.$procmux$1160_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$procmux$1194' using `$paramod$mux\WIDTH=3'.

            
            Mapping `usb_rx_phy.$procmux$1228' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_rx_phy.$procmux$1264' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_rx_phy.$procmux$1267' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_rx_phy.$procmux$1270' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_rx_phy.$procmux$1273' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_rx_phy.$procmux$1276' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_rx_phy.$procmux$1279' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_rx_phy.$procmux$1282' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_rx_phy.$procmux$1285' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_rx_phy.$procmux$1288' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_rx_phy.$procmux$1292' using `$paramod$mux\WIDTH=3'.

            
            Mapping `usb_rx_phy.$procmux$1294' using `$paramod$mux\WIDTH=3'.

            
            Mapping `usb_rx_phy.$procmux$1297' using `$paramod$mux\WIDTH=3'.

            
            Mapping `usb_rx_phy.$procmux$1300' using `$paramod$mux\WIDTH=3'.

            
            Mapping `usb_rx_phy.$procmux$1303' using `$paramod$mux\WIDTH=1'.


            10.46. Executing AST frontend in derive mode using pre-parsed AST for module `$mux'.

            
            Parameter \WIDTH = 8

            
            Generating RTLIL representation for module `$paramod$mux\WIDTH=8'.


            10.47. Continuing TECHMAP pass.

            
            Mapping `usb_rx_phy.$procmux$1306' using `$paramod$mux\WIDTH=8'.

            
            Mapping `usb_rx_phy.$procmux$1309' using `$paramod$mux\WIDTH=3'.

            
            Mapping `usb_rx_phy.$procmux$1312' using `$paramod$mux\WIDTH=3'.

            
            Mapping `usb_rx_phy.$procmux$1315' using `$paramod$mux\WIDTH=3'.

            
            Mapping `usb_rx_phy.$procmux$1318' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_rx_phy.$procmux$1321' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_rx_phy.$procmux$1324' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_rx_phy.$procmux$229' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_rx_phy.$procmux$232' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_rx_phy.$procmux$235' using `$paramod$mux\WIDTH=1'.


            10.48. Executing AST frontend in derive mode using pre-parsed AST for module `$mux'.

            
            Parameter \WIDTH = 2

            
            Generating RTLIL representation for module `$paramod$mux\WIDTH=2'.


            10.49. Continuing TECHMAP pass.

            
            Mapping `usb_rx_phy.$procmux$238' using `$paramod$mux\WIDTH=2'.

            
            Mapping `usb_rx_phy.$procmux$272' using `$paramod$mux\WIDTH=1'.


            10.50. Executing AST frontend in derive mode using pre-parsed AST for module `$eq'.

            
            Parameter \A_SIGNED = 0

            
            Parameter \B_SIGNED = 0

            
            Parameter \A_WIDTH = 2

            
            Parameter \B_WIDTH = 2

            
            Parameter \Y_WIDTH = 1

            
            Generating RTLIL representation for module `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=1'.


            10.51. Continuing TECHMAP pass.

            
            Mapping `usb_rx_phy.$procmux$273_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$procmux$277_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=1'.


            10.52. Executing AST frontend in derive mode using pre-parsed AST for module `$pmux'.

            
            Parameter \WIDTH = 2

            
            Parameter \S_WIDTH = 3

            
            Generating RTLIL representation for module `$paramod$pmux\WIDTH=2\S_WIDTH=3'.


            10.53. Continuing TECHMAP pass.

            
            Mapping `usb_rx_phy.$procmux$283' using `$paramod$pmux\WIDTH=2\S_WIDTH=3'.

            
            Mapping `usb_rx_phy.$procmux$284_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$procmux$303' using `$paramod$mux\WIDTH=2'.

            
            Mapping `usb_rx_phy.$procmux$314' using `$paramod$mux\WIDTH=2'.

            
            Mapping `usb_rx_phy.$procmux$326' using `$paramod$mux\WIDTH=2'.

            
            Mapping `usb_rx_phy.$procmux$354' using `$paramod$mux\WIDTH=3'.

            
            Mapping `usb_rx_phy.$procmux$467' using `$paramod$mux\WIDTH=3'.

            
            Mapping `usb_rx_phy.$procmux$496' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_rx_phy.$procmux$525' using `$paramod$mux\WIDTH=1'.


            10.54. Executing AST frontend in derive mode using pre-parsed AST for module `$pmux'.

            
            Parameter \WIDTH = 1

            
            Parameter \S_WIDTH = 3

            
            Generating RTLIL representation for module `$paramod$pmux\WIDTH=1\S_WIDTH=3'.


            10.55. Continuing TECHMAP pass.

            
            Mapping `usb_rx_phy.$procmux$533' using `$paramod$pmux\WIDTH=1\S_WIDTH=3'.


            10.56. Executing AST frontend in derive mode using pre-parsed AST for module `$pmux'.

            
            Parameter \WIDTH = 1

            
            Parameter \S_WIDTH = 2

            
            Generating RTLIL representation for module `$paramod$pmux\WIDTH=1\S_WIDTH=2'.


            10.57. Continuing TECHMAP pass.

            
            Mapping `usb_rx_phy.$procmux$569' using `$paramod$pmux\WIDTH=1\S_WIDTH=2'.


            10.58. Executing AST frontend in derive mode using pre-parsed AST for module `$pmux'.

            
            Parameter \WIDTH = 3

            
            Parameter \S_WIDTH = 7

            
            Generating RTLIL representation for module `$paramod$pmux\WIDTH=3\S_WIDTH=7'.


            10.59. Continuing TECHMAP pass.

            
            Mapping `usb_rx_phy.$procmux$605' using `$paramod$pmux\WIDTH=3\S_WIDTH=7'.

            
            Mapping `usb_rx_phy.$procmux$660' using `$paramod$mux\WIDTH=3'.

            
            Mapping `usb_rx_phy.$procmux$688' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_rx_phy.$procmux$720' using `$paramod$mux\WIDTH=3'.

            
            Mapping `usb_rx_phy.$procmux$782' using `$paramod$mux\WIDTH=3'.

            
            Mapping `usb_rx_phy.$procmux$846' using `$paramod$mux\WIDTH=3'.

            
            Mapping `usb_rx_phy.$procmux$912' using `$paramod$mux\WIDTH=3'.

            
            Mapping `usb_rx_phy.$procmux$944' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_rx_phy.$procmux$980' using `$paramod$mux\WIDTH=1'.


            10.60. Executing AST frontend in derive mode using pre-parsed AST for module `$reduce_or'.

            
            Parameter \A_SIGNED = 0

            
            Parameter \A_WIDTH = 2

            
            Parameter \Y_WIDTH = 1

            
            Generating RTLIL representation for module `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'.


            10.61. Continuing TECHMAP pass.

            
            Mapping `usb_rx_phy.$reduce_or$rtl/usb_rx_phy.v:449$127' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'.


            10.62. Executing AST frontend in derive mode using pre-parsed AST for module `$xor'.

            
            Parameter \A_SIGNED = 0

            
            Parameter \B_SIGNED = 0

            
            Parameter \A_WIDTH = 1

            
            Parameter \B_WIDTH = 1

            
            Parameter \Y_WIDTH = 1

            
            Generating RTLIL representation for module `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.


            10.63. Continuing TECHMAP pass.

            
            Mapping `usb_rx_phy.$xor$rtl/usb_rx_phy.v:380$83' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$add$rtl/usb_tx_phy.v:210$148' using `$paramod$add\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$add$rtl/usb_tx_phy.v:261$165' using `$paramod$add\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$and$rtl/usb_tx_phy.v:152$132' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$and$rtl/usb_tx_phy.v:229$154' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$and$rtl/usb_tx_phy.v:234$157' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$and$rtl/usb_tx_phy.v:333$188' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$and$rtl/usb_tx_phy.v:391$203' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$and$rtl/usb_tx_phy.v:402$209' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$eq$rtl/usb_tx_phy.v:229$153' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$eq$rtl/usb_tx_phy.v:264$166' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$logic_and$rtl/usb_tx_phy.v:192$141' using `$paramod$logic_and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$logic_and$rtl/usb_tx_phy.v:210$147' using `$paramod$logic_and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$logic_and$rtl/usb_tx_phy.v:443$215' using `$paramod$logic_and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$logic_and$rtl/usb_tx_phy.v:449$216' using `$paramod$logic_and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$logic_and$rtl/usb_tx_phy.v:458$218' using `$paramod$logic_and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$logic_not$rtl/usb_tx_phy.v:151$131' using `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$logic_not$rtl/usb_tx_phy.v:192$140' using `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$logic_not$rtl/usb_tx_phy.v:194$142' using `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$logic_not$rtl/usb_tx_phy.v:208$145' using `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$logic_not$rtl/usb_tx_phy.v:210$146' using `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$logic_not$rtl/usb_tx_phy.v:234$156' using `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$logic_not$rtl/usb_tx_phy.v:260$163' using `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$logic_not$rtl/usb_tx_phy.v:287$175' using `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$logic_not$rtl/usb_tx_phy.v:333$187' using `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$logic_not$rtl/usb_tx_phy.v:376$199' using `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$logic_not$rtl/usb_tx_phy.v:391$202' using `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$logic_not$rtl/usb_tx_phy.v:443$214' using `$paramod$logic_not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$logic_or$rtl/usb_tx_phy.v:260$164' using `$paramod$logic_or\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$logic_or$rtl/usb_tx_phy.v:287$176' using `$paramod$logic_or\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.


            10.64. Executing AST frontend in derive mode using pre-parsed AST for module `$not'.

            
            Parameter \A_SIGNED = 0

            
            Parameter \A_WIDTH = 1

            
            Parameter \Y_WIDTH = 1

            
            Generating RTLIL representation for module `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.


            10.65. Continuing TECHMAP pass.

            
            Mapping `usb_tx_phy.$not$rtl/usb_tx_phy.v:289$177' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$or$rtl/usb_tx_phy.v:333$189' using `$paramod$or\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$or$rtl/usb_tx_phy.v:376$198' using `$paramod$or\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$procdff$2015' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.

            
            Mapping `usb_tx_phy.$procdff$2016' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.

            
            Mapping `usb_tx_phy.$procdff$2017' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.

            
            Mapping `usb_tx_phy.$procdff$2018' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.

            
            Mapping `usb_tx_phy.$procdff$2019' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.

            
            Mapping `usb_tx_phy.$procdff$2020' using `$paramod$dff\WIDTH=3\CLK_POLARITY=1'1'.

            
            Mapping `usb_tx_phy.$procdff$2021' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.

            
            Mapping `usb_tx_phy.$procdff$2022' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.

            
            Mapping `usb_tx_phy.$procdff$2023' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.

            
            Mapping `usb_tx_phy.$procdff$2024' using `$paramod$dff\WIDTH=8\CLK_POLARITY=1'1'.

            
            Mapping `usb_tx_phy.$procdff$2025' using `$paramod$dff\WIDTH=8\CLK_POLARITY=1'1'.

            
            Mapping `usb_tx_phy.$procdff$2026' using `$paramod$dff\WIDTH=3\CLK_POLARITY=1'1'.

            
            Mapping `usb_tx_phy.$procdff$2027' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.

            
            Mapping `usb_tx_phy.$procdff$2028' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.

            
            Mapping `usb_tx_phy.$procdff$2029' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.

            
            Mapping `usb_tx_phy.$procdff$2030' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.

            
            Mapping `usb_tx_phy.$procdff$2031' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.

            
            Mapping `usb_tx_phy.$procdff$2032' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.

            
            Mapping `usb_tx_phy.$procdff$2033' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.

            
            Mapping `usb_tx_phy.$procdff$2034' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.

            
            Mapping `usb_tx_phy.$procdff$2035' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.

            
            Mapping `usb_tx_phy.$procdff$2036' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.

            
            Mapping `usb_tx_phy.$procdff$2037' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.

            
            Mapping `usb_tx_phy.$procdff$2038' using `$paramod$dff\WIDTH=1\CLK_POLARITY=1'1'.

            
            Mapping `usb_tx_phy.$procdff$2039' using `$paramod$dff\WIDTH=3\CLK_POLARITY=1'1'.

            
            Mapping `usb_tx_phy.$procmux$1327' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1330' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1333' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1336' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1339' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1342' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1345' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1348' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1351' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1354' using `$paramod$mux\WIDTH=3'.

            
            Mapping `usb_tx_phy.$procmux$1357' using `$paramod$mux\WIDTH=3'.

            
            Mapping `usb_tx_phy.$procmux$1360' using `$paramod$mux\WIDTH=3'.


            10.66. Executing AST frontend in derive mode using pre-parsed AST for module `$pmux'.

            
            Parameter \WIDTH = 1

            
            Parameter \S_WIDTH = 7

            
            Generating RTLIL representation for module `$paramod$pmux\WIDTH=1\S_WIDTH=7'.


            10.67. Continuing TECHMAP pass.

            
            Mapping `usb_tx_phy.$procmux$1363' using `$paramod$pmux\WIDTH=1\S_WIDTH=7'.

            
            Mapping `usb_tx_phy.$procmux$1364_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1366_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1368_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1370_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1372_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1374_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1376_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1378' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1381' using `$paramod$mux\WIDTH=8'.

            
            Mapping `usb_tx_phy.$procmux$1384' using `$paramod$mux\WIDTH=8'.

            
            Mapping `usb_tx_phy.$procmux$1388' using `$paramod$mux\WIDTH=3'.

            
            Mapping `usb_tx_phy.$procmux$1390' using `$paramod$mux\WIDTH=3'.

            
            Mapping `usb_tx_phy.$procmux$1393' using `$paramod$mux\WIDTH=3'.

            
            Mapping `usb_tx_phy.$procmux$1396' using `$paramod$mux\WIDTH=3'.

            
            Mapping `usb_tx_phy.$procmux$1399' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1402' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1405' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1408' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1411' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1414' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1417' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1420' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1423' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1426' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1429' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1432' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1435' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1438' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1441' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1444' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1447' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1450' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1453' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1456' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1459' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1462' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1465' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1468' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1471' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1474' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1477' using `$paramod$mux\WIDTH=3'.

            
            Mapping `usb_tx_phy.$procmux$1592' using `$paramod$pmux\WIDTH=1\S_WIDTH=2'.

            
            Mapping `usb_tx_phy.$procmux$1593_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1597_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1601_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1615' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1667' using `$paramod$mux\WIDTH=1'.


            10.68. Executing AST frontend in derive mode using pre-parsed AST for module `$pmux'.

            
            Parameter \WIDTH = 3

            
            Parameter \S_WIDTH = 5

            
            Generating RTLIL representation for module `$paramod$pmux\WIDTH=3\S_WIDTH=5'.


            10.69. Continuing TECHMAP pass.

            
            Mapping `usb_tx_phy.$procmux$1674' using `$paramod$pmux\WIDTH=3\S_WIDTH=5'.

            
            Mapping `usb_tx_phy.$procmux$1675_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1679_CMP0' using `$paramod$eq\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1712' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1734' using `$paramod$mux\WIDTH=3'.

            
            Mapping `usb_tx_phy.$procmux$1753' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1799' using `$paramod$mux\WIDTH=3'.

            
            Mapping `usb_tx_phy.$procmux$1817' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1841' using `$paramod$mux\WIDTH=3'.

            
            Mapping `usb_tx_phy.$procmux$1867' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1910' using `$paramod$mux\WIDTH=3'.

            
            Mapping `usb_tx_phy.$procmux$1932' using `$paramod$mux\WIDTH=3'.

            
            Mapping `usb_tx_phy.$procmux$1955' using `$paramod$mux\WIDTH=3'.

            
            Mapping `usb_tx_phy.$ternary$rtl/usb_tx_phy.v:273$170' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_tx_phy.$ternary$rtl/usb_tx_phy.v:273$171' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_tx_phy.$ternary$rtl/usb_tx_phy.v:289$178' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_tx_phy.$ternary$rtl/usb_tx_phy.v:392$204' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_tx_phy.$ternary$rtl/usb_tx_phy.v:403$210' using `$paramod$mux\WIDTH=1'.


            10.70. Executing AST frontend in derive mode using pre-parsed AST for module `$pos'.

            
            Parameter \A_SIGNED = 1'0

            
            Parameter \A_WIDTH = 5

            
            Parameter \Y_WIDTH = 5

            
            Generating RTLIL representation for module `$paramod$pos\A_SIGNED=1'0\A_WIDTH=5\Y_WIDTH=5'.


            10.71. Continuing TECHMAP pass.

            
            Mapping `usb_phy.$add$rtl/usb_phy.v:178$6.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=5\Y_WIDTH=5'.

            
            Mapping `usb_phy.$add$rtl/usb_phy.v:178$6.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=5\Y_WIDTH=5'.


            10.72. Executing AST frontend in derive mode using pre-parsed AST for module `$alu'.

            
            Parameter \WIDTH = 5

            
            Generating RTLIL representation for module `$paramod$alu\WIDTH=5'.


            10.73. Continuing TECHMAP pass.

            
            Mapping `usb_phy.$add$rtl/usb_phy.v:178$6.alu' using `$paramod$alu\WIDTH=5'.

            
            Mapping `usb_phy.$eq$rtl/usb_phy.v:181$8.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=5\Y_WIDTH=5'.

            
            Mapping `usb_phy.$eq$rtl/usb_phy.v:181$8.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=5\Y_WIDTH=5'.


            10.74. Executing AST frontend in derive mode using pre-parsed AST for module `$reduce_bool'.

            
            Parameter \A_SIGNED = 0

            
            Parameter \A_WIDTH = 1

            
            Generating RTLIL representation for module `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.


            10.75. Continuing TECHMAP pass.

            
            Mapping `usb_phy.$logic_and$rtl/usb_phy.v:178$5.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_phy.$logic_and$rtl/usb_phy.v:178$5.B_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_phy.$logic_not$rtl/usb_phy.v:174$2.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_phy.$logic_not$rtl/usb_phy.v:178$4.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.


            10.76. Executing AST frontend in derive mode using pre-parsed AST for module `$pos'.

            
            Parameter \A_SIGNED = 1'0

            
            Parameter \A_WIDTH = 2

            
            Parameter \Y_WIDTH = 2

            
            Generating RTLIL representation for module `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'.


            10.77. Continuing TECHMAP pass.

            
            Mapping `usb_phy.$ne$rtl/usb_phy.v:176$3.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'.

            
            Mapping `usb_phy.$ne$rtl/usb_phy.v:176$3.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'.

            
            Mapping `usb_phy.$techmap$eq$rtl/usb_phy.v:181$8.$not$<stdcells.v>:808$2075' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.


            10.78. Executing AST frontend in derive mode using pre-parsed AST for module `$reduce_or'.

            
            Parameter \A_SIGNED = 0

            
            Parameter \A_WIDTH = 5

            
            Parameter \Y_WIDTH = 1

            
            Generating RTLIL representation for module `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=5\Y_WIDTH=1'.


            10.79. Continuing TECHMAP pass.

            
            Mapping `usb_phy.$techmap$eq$rtl/usb_phy.v:181$8.$reduce_or$<stdcells.v>:808$2074' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=5\Y_WIDTH=1'.


            10.80. Executing AST frontend in derive mode using pre-parsed AST for module `$xor'.

            
            Parameter \A_SIGNED = 0

            
            Parameter \B_SIGNED = 0

            
            Parameter \A_WIDTH = 5

            
            Parameter \B_WIDTH = 5

            
            Parameter \Y_WIDTH = 5

            
            Generating RTLIL representation for module `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=5\Y_WIDTH=5'.


            10.81. Continuing TECHMAP pass.

            
            Mapping `usb_phy.$techmap$eq$rtl/usb_phy.v:181$8.$xor$<stdcells.v>:808$2073' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=5\B_WIDTH=5\Y_WIDTH=5'.

            
            Mapping `usb_phy.$techmap$ne$rtl/usb_phy.v:176$3.$reduce_or$<stdcells.v>:833$2077' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'.


            10.82. Executing AST frontend in derive mode using pre-parsed AST for module `$xor'.

            
            Parameter \A_SIGNED = 0

            
            Parameter \B_SIGNED = 0

            
            Parameter \A_WIDTH = 2

            
            Parameter \B_WIDTH = 2

            
            Parameter \Y_WIDTH = 2

            
            Generating RTLIL representation for module `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'.


            10.83. Continuing TECHMAP pass.

            
            Mapping `usb_phy.$techmap$ne$rtl/usb_phy.v:176$3.$xor$<stdcells.v>:833$2076' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'.


            10.84. Executing AST frontend in derive mode using pre-parsed AST for module `$pos'.

            
            Parameter \A_SIGNED = 1'0

            
            Parameter \A_WIDTH = 3

            
            Parameter \Y_WIDTH = 3

            
            Generating RTLIL representation for module `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.


            10.85. Continuing TECHMAP pass.

            
            Mapping `usb_rx_phy.$add$rtl/usb_rx_phy.v:399$90.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$add$rtl/usb_rx_phy.v:399$90.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.


            10.86. Executing AST frontend in derive mode using pre-parsed AST for module `$alu'.

            
            Parameter \WIDTH = 3

            
            Generating RTLIL representation for module `$paramod$alu\WIDTH=3'.


            10.87. Continuing TECHMAP pass.

            
            Mapping `usb_rx_phy.$add$rtl/usb_rx_phy.v:399$90.alu' using `$paramod$alu\WIDTH=3'.

            
            Mapping `usb_rx_phy.$add$rtl/usb_rx_phy.v:432$109.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$add$rtl/usb_rx_phy.v:432$109.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$add$rtl/usb_rx_phy.v:432$109.alu' using `$paramod$alu\WIDTH=3'.


            10.88. Executing AST frontend in derive mode using pre-parsed AST for module `$pos'.

            
            Parameter \A_SIGNED = 0

            
            Parameter \A_WIDTH = 1

            
            Parameter \Y_WIDTH = 1

            
            Generating RTLIL representation for module `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.


            10.89. Continuing TECHMAP pass.

            
            Mapping `usb_rx_phy.$and$rtl/usb_rx_phy.v:145$14.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$and$rtl/usb_rx_phy.v:145$14.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$and$rtl/usb_rx_phy.v:166$25.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$and$rtl/usb_rx_phy.v:166$25.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$and$rtl/usb_rx_phy.v:171$32.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$and$rtl/usb_rx_phy.v:171$32.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$and$rtl/usb_rx_phy.v:174$37.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$and$rtl/usb_rx_phy.v:174$37.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$and$rtl/usb_rx_phy.v:175$39.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$and$rtl/usb_rx_phy.v:175$39.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$and$rtl/usb_rx_phy.v:176$42.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$and$rtl/usb_rx_phy.v:176$42.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$and$rtl/usb_rx_phy.v:404$93.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$and$rtl/usb_rx_phy.v:404$93.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$and$rtl/usb_rx_phy.v:404$94.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$and$rtl/usb_rx_phy.v:404$94.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$and$rtl/usb_rx_phy.v:404$96.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$and$rtl/usb_rx_phy.v:404$96.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$and$rtl/usb_rx_phy.v:404$97.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$and$rtl/usb_rx_phy.v:404$97.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$and$rtl/usb_rx_phy.v:445$121.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$and$rtl/usb_rx_phy.v:445$121.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$and$rtl/usb_rx_phy.v:445$122.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$and$rtl/usb_rx_phy.v:445$122.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$and$rtl/usb_rx_phy.v:449$126.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$and$rtl/usb_rx_phy.v:449$126.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$and$rtl/usb_rx_phy.v:449$128.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$and$rtl/usb_rx_phy.v:449$128.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$and$rtl/usb_rx_phy.v:449$129.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$and$rtl/usb_rx_phy.v:449$129.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$eq$rtl/usb_rx_phy.v:402$91.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$eq$rtl/usb_rx_phy.v:402$91.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$eq$rtl/usb_rx_phy.v:441$114.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$eq$rtl/usb_rx_phy.v:441$114.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:160$18.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:160$18.B_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:162$21.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:162$21.B_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:216$49.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:216$49.B_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:268$60.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:268$60.B_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:268$62.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:268$62.B_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:268$64.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:268$64.B_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:272$65.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:272$65.B_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:276$66.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:276$66.B_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:354$75.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:354$75.B_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:356$76.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:356$76.B_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:380$82.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:380$82.B_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:415$101.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:415$101.B_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:415$103.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:415$103.B_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:432$108.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:432$108.B_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:441$115.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:441$115.B_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:443$116.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:443$116.B_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:443$118.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_and$rtl/usb_rx_phy.v:443$118.B_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_not$rtl/usb_rx_phy.v:145$13.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_not$rtl/usb_rx_phy.v:162$19.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_not$rtl/usb_rx_phy.v:162$20.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_not$rtl/usb_rx_phy.v:174$36.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_not$rtl/usb_rx_phy.v:175$38.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_not$rtl/usb_rx_phy.v:208$47.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_not$rtl/usb_rx_phy.v:268$61.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_not$rtl/usb_rx_phy.v:268$63.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_not$rtl/usb_rx_phy.v:380$84.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_not$rtl/usb_rx_phy.v:394$87.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_not$rtl/usb_rx_phy.v:398$88.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_not$rtl/usb_rx_phy.v:415$102.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_not$rtl/usb_rx_phy.v:449$125.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_or$rtl/usb_rx_phy.v:398$89.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_rx_phy.$logic_or$rtl/usb_rx_phy.v:398$89.B_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.


            10.90. Executing AST frontend in derive mode using pre-parsed AST for module `$pos'.

            
            Parameter \A_SIGNED = 1'0

            
            Parameter \A_WIDTH = 1

            
            Parameter \Y_WIDTH = 1

            
            Generating RTLIL representation for module `$paramod$pos\A_SIGNED=1'0\A_WIDTH=1\Y_WIDTH=1'.


            10.91. Continuing TECHMAP pass.

            
            Mapping `usb_rx_phy.$ne$rtl/usb_rx_phy.v:200$45.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$ne$rtl/usb_rx_phy.v:200$45.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$or$rtl/usb_rx_phy.v:140$10.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$or$rtl/usb_rx_phy.v:140$10.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$or$rtl/usb_rx_phy.v:140$9.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$or$rtl/usb_rx_phy.v:140$9.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$or$rtl/usb_rx_phy.v:167$28.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$or$rtl/usb_rx_phy.v:167$28.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$or$rtl/usb_rx_phy.v:172$35.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$or$rtl/usb_rx_phy.v:172$35.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$or$rtl/usb_rx_phy.v:412$99.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$or$rtl/usb_rx_phy.v:412$99.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$procmux$1003_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$procmux$1003_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$procmux$1019_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$procmux$1019_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$procmux$1023_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$procmux$1023_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$procmux$1027_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$procmux$1027_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$procmux$1031_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$procmux$1031_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$procmux$1035_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$procmux$1035_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$procmux$1160_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$procmux$1160_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$procmux$273_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'.

            
            Mapping `usb_rx_phy.$procmux$273_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'.

            
            Mapping `usb_rx_phy.$procmux$277_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'.

            
            Mapping `usb_rx_phy.$procmux$277_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'.

            
            Mapping `usb_rx_phy.$procmux$284_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'.

            
            Mapping `usb_rx_phy.$procmux$284_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=2\Y_WIDTH=2'.

            
            Mapping `usb_rx_phy.$techmap$eq$rtl/usb_rx_phy.v:402$91.$not$<stdcells.v>:808$2080' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.


            10.92. Executing AST frontend in derive mode using pre-parsed AST for module `$reduce_or'.

            
            Parameter \A_SIGNED = 0

            
            Parameter \A_WIDTH = 3

            
            Parameter \Y_WIDTH = 1

            
            Generating RTLIL representation for module `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'.


            10.93. Continuing TECHMAP pass.

            
            Mapping `usb_rx_phy.$techmap$eq$rtl/usb_rx_phy.v:402$91.$reduce_or$<stdcells.v>:808$2079' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'.


            10.94. Executing AST frontend in derive mode using pre-parsed AST for module `$xor'.

            
            Parameter \A_SIGNED = 0

            
            Parameter \B_SIGNED = 0

            
            Parameter \A_WIDTH = 3

            
            Parameter \B_WIDTH = 3

            
            Parameter \Y_WIDTH = 3

            
            Generating RTLIL representation for module `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'.


            10.95. Continuing TECHMAP pass.

            
            Mapping `usb_rx_phy.$techmap$eq$rtl/usb_rx_phy.v:402$91.$xor$<stdcells.v>:808$2078' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$techmap$eq$rtl/usb_rx_phy.v:441$114.$not$<stdcells.v>:808$2080' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$eq$rtl/usb_rx_phy.v:441$114.$reduce_or$<stdcells.v>:808$2079' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$eq$rtl/usb_rx_phy.v:441$114.$xor$<stdcells.v>:808$2078' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'.


            10.96. Executing AST frontend in derive mode using pre-parsed AST for module `$reduce_or'.

            
            Parameter \A_SIGNED = 0

            
            Parameter \A_WIDTH = 1

            
            Parameter \Y_WIDTH = 1

            
            Generating RTLIL representation for module `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.


            10.97. Continuing TECHMAP pass.

            
            Mapping `usb_rx_phy.$techmap$ne$rtl/usb_rx_phy.v:200$45.$reduce_or$<stdcells.v>:833$2082' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$ne$rtl/usb_rx_phy.v:200$45.$xor$<stdcells.v>:833$2081' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$1003_CMP0.$not$<stdcells.v>:808$2080' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$1003_CMP0.$reduce_or$<stdcells.v>:808$2079' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$1003_CMP0.$xor$<stdcells.v>:808$2078' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$techmap$procmux$1019_CMP0.$not$<stdcells.v>:808$2080' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$1019_CMP0.$reduce_or$<stdcells.v>:808$2079' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$1019_CMP0.$xor$<stdcells.v>:808$2078' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$techmap$procmux$1023_CMP0.$not$<stdcells.v>:808$2080' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$1023_CMP0.$reduce_or$<stdcells.v>:808$2079' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$1023_CMP0.$xor$<stdcells.v>:808$2078' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$techmap$procmux$1027_CMP0.$not$<stdcells.v>:808$2080' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$1027_CMP0.$reduce_or$<stdcells.v>:808$2079' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$1027_CMP0.$xor$<stdcells.v>:808$2078' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$techmap$procmux$1031_CMP0.$not$<stdcells.v>:808$2080' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$1031_CMP0.$reduce_or$<stdcells.v>:808$2079' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$1031_CMP0.$xor$<stdcells.v>:808$2078' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$techmap$procmux$1035_CMP0.$not$<stdcells.v>:808$2080' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$1035_CMP0.$reduce_or$<stdcells.v>:808$2079' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$1035_CMP0.$xor$<stdcells.v>:808$2078' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$techmap$procmux$1160_CMP0.$not$<stdcells.v>:808$2080' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$1160_CMP0.$reduce_or$<stdcells.v>:808$2079' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$1160_CMP0.$xor$<stdcells.v>:808$2078' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$techmap$procmux$273_CMP0.$not$<stdcells.v>:808$2085' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$273_CMP0.$reduce_or$<stdcells.v>:808$2084' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$273_CMP0.$xor$<stdcells.v>:808$2083' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'.

            
            Mapping `usb_rx_phy.$techmap$procmux$277_CMP0.$not$<stdcells.v>:808$2085' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$277_CMP0.$reduce_or$<stdcells.v>:808$2084' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$277_CMP0.$xor$<stdcells.v>:808$2083' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'.


            10.98. Executing AST frontend in derive mode using pre-parsed AST for module `$and'.

            
            Parameter \A_SIGNED = 0

            
            Parameter \B_SIGNED = 0

            
            Parameter \A_WIDTH = 2

            
            Parameter \B_WIDTH = 2

            
            Parameter \Y_WIDTH = 2

            
            Generating RTLIL representation for module `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'.


            10.99. Continuing TECHMAP pass.

            
            Mapping `usb_rx_phy.$techmap$procmux$283.$and$<stdcells.v>:1203$2088' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'.

            
            Mapping `usb_rx_phy.$techmap$procmux$283.$and$<stdcells.v>:1203$2089' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'.

            
            Mapping `usb_rx_phy.$techmap$procmux$283.$and$<stdcells.v>:1203$2090' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'.

            
            Mapping `usb_rx_phy.$techmap$procmux$283.$reduce_or$<stdcells.v>:1210$2091' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$283.$reduce_or$<stdcells.v>:1210$2092' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$283.$reduce_or$<stdcells.v>:1214$2086' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$283.$ternary$<stdcells.v>:1214$2087' using `$paramod$mux\WIDTH=2'.

            
            Mapping `usb_rx_phy.$techmap$procmux$284_CMP0.$not$<stdcells.v>:808$2085' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$284_CMP0.$reduce_or$<stdcells.v>:808$2084' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$284_CMP0.$xor$<stdcells.v>:808$2083' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=2\B_WIDTH=2\Y_WIDTH=2'.

            
            Mapping `usb_rx_phy.$techmap$procmux$533.$and$<stdcells.v>:1203$2095' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$533.$and$<stdcells.v>:1203$2096' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$533.$and$<stdcells.v>:1203$2097' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$533.$reduce_or$<stdcells.v>:1210$2098' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$533.$reduce_or$<stdcells.v>:1214$2093' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$533.$ternary$<stdcells.v>:1214$2094' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$569.$and$<stdcells.v>:1203$2101' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$569.$and$<stdcells.v>:1203$2102' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$569.$reduce_or$<stdcells.v>:1210$2103' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$569.$reduce_or$<stdcells.v>:1214$2099' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$569.$ternary$<stdcells.v>:1214$2100' using `$paramod$mux\WIDTH=1'.


            10.100. Executing AST frontend in derive mode using pre-parsed AST for module `$and'.

            
            Parameter \A_SIGNED = 0

            
            Parameter \B_SIGNED = 0

            
            Parameter \A_WIDTH = 3

            
            Parameter \B_WIDTH = 3

            
            Parameter \Y_WIDTH = 3

            
            Generating RTLIL representation for module `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'.


            10.101. Continuing TECHMAP pass.

            
            Mapping `usb_rx_phy.$techmap$procmux$605.$and$<stdcells.v>:1203$2106' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$techmap$procmux$605.$and$<stdcells.v>:1203$2107' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$techmap$procmux$605.$and$<stdcells.v>:1203$2108' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$techmap$procmux$605.$and$<stdcells.v>:1203$2109' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$techmap$procmux$605.$and$<stdcells.v>:1203$2110' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$techmap$procmux$605.$and$<stdcells.v>:1203$2111' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$techmap$procmux$605.$and$<stdcells.v>:1203$2112' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'.


            10.102. Executing AST frontend in derive mode using pre-parsed AST for module `$reduce_or'.

            
            Parameter \A_SIGNED = 0

            
            Parameter \A_WIDTH = 7

            
            Parameter \Y_WIDTH = 1

            
            Generating RTLIL representation for module `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=7\Y_WIDTH=1'.


            10.103. Continuing TECHMAP pass.

            
            Mapping `usb_rx_phy.$techmap$procmux$605.$reduce_or$<stdcells.v>:1210$2113' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=7\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$605.$reduce_or$<stdcells.v>:1210$2114' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=7\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$605.$reduce_or$<stdcells.v>:1210$2115' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=7\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$605.$reduce_or$<stdcells.v>:1214$2104' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=7\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$605.$ternary$<stdcells.v>:1214$2105' using `$paramod$mux\WIDTH=3'.

            
            Mapping `usb_rx_phy.$xor$rtl/usb_rx_phy.v:380$83.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$xor$rtl/usb_rx_phy.v:380$83.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$add$rtl/usb_tx_phy.v:210$148.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$add$rtl/usb_tx_phy.v:210$148.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$add$rtl/usb_tx_phy.v:210$148.alu' using `$paramod$alu\WIDTH=3'.

            
            Mapping `usb_tx_phy.$add$rtl/usb_tx_phy.v:261$165.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$add$rtl/usb_tx_phy.v:261$165.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$add$rtl/usb_tx_phy.v:261$165.alu' using `$paramod$alu\WIDTH=3'.

            
            Mapping `usb_tx_phy.$and$rtl/usb_tx_phy.v:152$132.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$and$rtl/usb_tx_phy.v:152$132.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$and$rtl/usb_tx_phy.v:229$154.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$and$rtl/usb_tx_phy.v:229$154.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$and$rtl/usb_tx_phy.v:234$157.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$and$rtl/usb_tx_phy.v:234$157.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$and$rtl/usb_tx_phy.v:333$188.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$and$rtl/usb_tx_phy.v:333$188.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$and$rtl/usb_tx_phy.v:391$203.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$and$rtl/usb_tx_phy.v:391$203.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$and$rtl/usb_tx_phy.v:402$209.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$and$rtl/usb_tx_phy.v:402$209.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$eq$rtl/usb_tx_phy.v:229$153.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$eq$rtl/usb_tx_phy.v:229$153.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$eq$rtl/usb_tx_phy.v:264$166.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$eq$rtl/usb_tx_phy.v:264$166.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$logic_and$rtl/usb_tx_phy.v:192$141.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_tx_phy.$logic_and$rtl/usb_tx_phy.v:192$141.B_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_tx_phy.$logic_and$rtl/usb_tx_phy.v:210$147.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_tx_phy.$logic_and$rtl/usb_tx_phy.v:210$147.B_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_tx_phy.$logic_and$rtl/usb_tx_phy.v:443$215.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_tx_phy.$logic_and$rtl/usb_tx_phy.v:443$215.B_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_tx_phy.$logic_and$rtl/usb_tx_phy.v:449$216.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_tx_phy.$logic_and$rtl/usb_tx_phy.v:449$216.B_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_tx_phy.$logic_and$rtl/usb_tx_phy.v:458$218.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_tx_phy.$logic_and$rtl/usb_tx_phy.v:458$218.B_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_tx_phy.$logic_not$rtl/usb_tx_phy.v:151$131.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_tx_phy.$logic_not$rtl/usb_tx_phy.v:192$140.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_tx_phy.$logic_not$rtl/usb_tx_phy.v:194$142.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_tx_phy.$logic_not$rtl/usb_tx_phy.v:208$145.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_tx_phy.$logic_not$rtl/usb_tx_phy.v:210$146.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_tx_phy.$logic_not$rtl/usb_tx_phy.v:234$156.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_tx_phy.$logic_not$rtl/usb_tx_phy.v:260$163.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_tx_phy.$logic_not$rtl/usb_tx_phy.v:287$175.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_tx_phy.$logic_not$rtl/usb_tx_phy.v:333$187.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_tx_phy.$logic_not$rtl/usb_tx_phy.v:376$199.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_tx_phy.$logic_not$rtl/usb_tx_phy.v:391$202.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_tx_phy.$logic_not$rtl/usb_tx_phy.v:443$214.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_tx_phy.$logic_or$rtl/usb_tx_phy.v:260$164.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_tx_phy.$logic_or$rtl/usb_tx_phy.v:260$164.B_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_tx_phy.$logic_or$rtl/usb_tx_phy.v:287$176.A_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_tx_phy.$logic_or$rtl/usb_tx_phy.v:287$176.B_logic' using `$paramod$reduce_bool\A_SIGNED=0\A_WIDTH=1'.

            
            Mapping `usb_tx_phy.$or$rtl/usb_tx_phy.v:333$189.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$or$rtl/usb_tx_phy.v:333$189.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$or$rtl/usb_tx_phy.v:376$198.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$or$rtl/usb_tx_phy.v:376$198.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$procmux$1364_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$procmux$1364_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$procmux$1366_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$procmux$1366_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$procmux$1368_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$procmux$1368_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$procmux$1370_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$procmux$1370_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$procmux$1372_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$procmux$1372_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$procmux$1374_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$procmux$1374_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$procmux$1376_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$procmux$1376_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$procmux$1593_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$procmux$1593_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$procmux$1597_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$procmux$1597_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$procmux$1601_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$procmux$1601_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$procmux$1675_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$procmux$1675_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$procmux$1679_CMP0.A_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$procmux$1679_CMP0.B_conv' using `$paramod$pos\A_SIGNED=1'0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$eq$rtl/usb_tx_phy.v:229$153.$not$<stdcells.v>:808$2080' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$eq$rtl/usb_tx_phy.v:229$153.$reduce_or$<stdcells.v>:808$2079' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$eq$rtl/usb_tx_phy.v:229$153.$xor$<stdcells.v>:808$2078' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$eq$rtl/usb_tx_phy.v:264$166.$not$<stdcells.v>:808$2080' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$eq$rtl/usb_tx_phy.v:264$166.$reduce_or$<stdcells.v>:808$2079' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$eq$rtl/usb_tx_phy.v:264$166.$xor$<stdcells.v>:808$2078' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1363.$and$<stdcells.v>:1203$2118' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1363.$and$<stdcells.v>:1203$2119' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1363.$and$<stdcells.v>:1203$2120' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1363.$and$<stdcells.v>:1203$2121' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1363.$and$<stdcells.v>:1203$2122' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1363.$and$<stdcells.v>:1203$2123' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1363.$and$<stdcells.v>:1203$2124' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1363.$reduce_or$<stdcells.v>:1210$2125' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=7\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1363.$reduce_or$<stdcells.v>:1214$2116' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=7\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1363.$ternary$<stdcells.v>:1214$2117' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1364_CMP0.$not$<stdcells.v>:808$2080' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1364_CMP0.$reduce_or$<stdcells.v>:808$2079' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1364_CMP0.$xor$<stdcells.v>:808$2078' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1366_CMP0.$not$<stdcells.v>:808$2080' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1366_CMP0.$reduce_or$<stdcells.v>:808$2079' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1366_CMP0.$xor$<stdcells.v>:808$2078' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1368_CMP0.$not$<stdcells.v>:808$2080' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1368_CMP0.$reduce_or$<stdcells.v>:808$2079' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1368_CMP0.$xor$<stdcells.v>:808$2078' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1370_CMP0.$not$<stdcells.v>:808$2080' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1370_CMP0.$reduce_or$<stdcells.v>:808$2079' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1370_CMP0.$xor$<stdcells.v>:808$2078' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1372_CMP0.$not$<stdcells.v>:808$2080' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1372_CMP0.$reduce_or$<stdcells.v>:808$2079' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1372_CMP0.$xor$<stdcells.v>:808$2078' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1374_CMP0.$not$<stdcells.v>:808$2080' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1374_CMP0.$reduce_or$<stdcells.v>:808$2079' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1374_CMP0.$xor$<stdcells.v>:808$2078' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1376_CMP0.$not$<stdcells.v>:808$2080' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1376_CMP0.$reduce_or$<stdcells.v>:808$2079' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1376_CMP0.$xor$<stdcells.v>:808$2078' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1592.$and$<stdcells.v>:1203$2101' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1592.$and$<stdcells.v>:1203$2102' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1592.$reduce_or$<stdcells.v>:1210$2103' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1592.$reduce_or$<stdcells.v>:1214$2099' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1592.$ternary$<stdcells.v>:1214$2100' using `$paramod$mux\WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1593_CMP0.$not$<stdcells.v>:808$2080' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1593_CMP0.$reduce_or$<stdcells.v>:808$2079' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1593_CMP0.$xor$<stdcells.v>:808$2078' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1597_CMP0.$not$<stdcells.v>:808$2080' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1597_CMP0.$reduce_or$<stdcells.v>:808$2079' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1597_CMP0.$xor$<stdcells.v>:808$2078' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1601_CMP0.$not$<stdcells.v>:808$2080' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1601_CMP0.$reduce_or$<stdcells.v>:808$2079' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1601_CMP0.$xor$<stdcells.v>:808$2078' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1674.$and$<stdcells.v>:1203$2128' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1674.$and$<stdcells.v>:1203$2129' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1674.$and$<stdcells.v>:1203$2130' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1674.$and$<stdcells.v>:1203$2131' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1674.$and$<stdcells.v>:1203$2132' using `$paramod$and\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1674.$reduce_or$<stdcells.v>:1210$2133' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=5\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1674.$reduce_or$<stdcells.v>:1210$2134' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=5\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1674.$reduce_or$<stdcells.v>:1210$2135' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=5\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1674.$reduce_or$<stdcells.v>:1214$2126' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=5\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1674.$ternary$<stdcells.v>:1214$2127' using `$paramod$mux\WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1675_CMP0.$not$<stdcells.v>:808$2080' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1675_CMP0.$reduce_or$<stdcells.v>:808$2079' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1675_CMP0.$xor$<stdcells.v>:808$2078' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1679_CMP0.$not$<stdcells.v>:808$2080' using `$paramod$not\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1679_CMP0.$reduce_or$<stdcells.v>:808$2079' using `$paramod$reduce_or\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1679_CMP0.$xor$<stdcells.v>:808$2078' using `$paramod$xor\A_SIGNED=0\B_SIGNED=0\A_WIDTH=3\B_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_phy.$add$rtl/usb_phy.v:178$6.alu.V[0].adder' using `$fulladd'.

            
            Mapping `usb_phy.$add$rtl/usb_phy.v:178$6.alu.V[1].adder' using `$fulladd'.

            
            Mapping `usb_phy.$add$rtl/usb_phy.v:178$6.alu.V[2].adder' using `$fulladd'.

            
            Mapping `usb_phy.$add$rtl/usb_phy.v:178$6.alu.V[3].adder' using `$fulladd'.

            
            Mapping `usb_phy.$add$rtl/usb_phy.v:178$6.alu.V[4].adder' using `$fulladd'.


            10.104. Executing AST frontend in derive mode using pre-parsed AST for module `$pos'.

            
            Parameter \A_SIGNED = 0

            
            Parameter \A_WIDTH = 5

            
            Parameter \Y_WIDTH = 5

            
            Generating RTLIL representation for module `$paramod$pos\A_SIGNED=0\A_WIDTH=5\Y_WIDTH=5'.


            10.105. Continuing TECHMAP pass.

            
            Mapping `usb_phy.$techmap$eq$rtl/usb_phy.v:181$8.$xor$<stdcells.v>:808$2073.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=5\Y_WIDTH=5'.

            
            Mapping `usb_phy.$techmap$eq$rtl/usb_phy.v:181$8.$xor$<stdcells.v>:808$2073.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=5\Y_WIDTH=5'.


            10.106. Executing AST frontend in derive mode using pre-parsed AST for module `$pos'.

            
            Parameter \A_SIGNED = 0

            
            Parameter \A_WIDTH = 2

            
            Parameter \Y_WIDTH = 2

            
            Generating RTLIL representation for module `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'.


            10.107. Continuing TECHMAP pass.

            
            Mapping `usb_phy.$techmap$ne$rtl/usb_phy.v:176$3.$xor$<stdcells.v>:833$2076.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'.

            
            Mapping `usb_phy.$techmap$ne$rtl/usb_phy.v:176$3.$xor$<stdcells.v>:833$2076.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'.

            
            Mapping `usb_rx_phy.$add$rtl/usb_rx_phy.v:399$90.alu.V[0].adder' using `$fulladd'.

            
            Mapping `usb_rx_phy.$add$rtl/usb_rx_phy.v:399$90.alu.V[1].adder' using `$fulladd'.

            
            Mapping `usb_rx_phy.$add$rtl/usb_rx_phy.v:399$90.alu.V[2].adder' using `$fulladd'.

            
            Mapping `usb_rx_phy.$add$rtl/usb_rx_phy.v:432$109.alu.V[0].adder' using `$fulladd'.

            
            Mapping `usb_rx_phy.$add$rtl/usb_rx_phy.v:432$109.alu.V[1].adder' using `$fulladd'.

            
            Mapping `usb_rx_phy.$add$rtl/usb_rx_phy.v:432$109.alu.V[2].adder' using `$fulladd'.


            10.108. Executing AST frontend in derive mode using pre-parsed AST for module `$pos'.

            
            Parameter \A_SIGNED = 0

            
            Parameter \A_WIDTH = 3

            
            Parameter \Y_WIDTH = 3

            
            Generating RTLIL representation for module `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.


            10.109. Continuing TECHMAP pass.

            
            Mapping `usb_rx_phy.$techmap$eq$rtl/usb_rx_phy.v:402$91.$xor$<stdcells.v>:808$2078.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$techmap$eq$rtl/usb_rx_phy.v:402$91.$xor$<stdcells.v>:808$2078.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$techmap$eq$rtl/usb_rx_phy.v:441$114.$xor$<stdcells.v>:808$2078.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$techmap$eq$rtl/usb_rx_phy.v:441$114.$xor$<stdcells.v>:808$2078.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$techmap$ne$rtl/usb_rx_phy.v:200$45.$xor$<stdcells.v>:833$2081.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$ne$rtl/usb_rx_phy.v:200$45.$xor$<stdcells.v>:833$2081.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$1003_CMP0.$xor$<stdcells.v>:808$2078.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$techmap$procmux$1003_CMP0.$xor$<stdcells.v>:808$2078.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$techmap$procmux$1019_CMP0.$xor$<stdcells.v>:808$2078.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$techmap$procmux$1019_CMP0.$xor$<stdcells.v>:808$2078.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$techmap$procmux$1023_CMP0.$xor$<stdcells.v>:808$2078.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$techmap$procmux$1023_CMP0.$xor$<stdcells.v>:808$2078.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$techmap$procmux$1027_CMP0.$xor$<stdcells.v>:808$2078.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$techmap$procmux$1027_CMP0.$xor$<stdcells.v>:808$2078.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$techmap$procmux$1031_CMP0.$xor$<stdcells.v>:808$2078.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$techmap$procmux$1031_CMP0.$xor$<stdcells.v>:808$2078.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$techmap$procmux$1035_CMP0.$xor$<stdcells.v>:808$2078.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$techmap$procmux$1035_CMP0.$xor$<stdcells.v>:808$2078.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$techmap$procmux$1160_CMP0.$xor$<stdcells.v>:808$2078.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$techmap$procmux$1160_CMP0.$xor$<stdcells.v>:808$2078.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$techmap$procmux$273_CMP0.$xor$<stdcells.v>:808$2083.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'.

            
            Mapping `usb_rx_phy.$techmap$procmux$273_CMP0.$xor$<stdcells.v>:808$2083.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'.

            
            Mapping `usb_rx_phy.$techmap$procmux$277_CMP0.$xor$<stdcells.v>:808$2083.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'.

            
            Mapping `usb_rx_phy.$techmap$procmux$277_CMP0.$xor$<stdcells.v>:808$2083.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'.

            
            Mapping `usb_rx_phy.$techmap$procmux$283.$and$<stdcells.v>:1203$2088.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'.

            
            Mapping `usb_rx_phy.$techmap$procmux$283.$and$<stdcells.v>:1203$2088.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'.

            
            Mapping `usb_rx_phy.$techmap$procmux$283.$and$<stdcells.v>:1203$2089.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'.

            
            Mapping `usb_rx_phy.$techmap$procmux$283.$and$<stdcells.v>:1203$2089.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'.

            
            Mapping `usb_rx_phy.$techmap$procmux$283.$and$<stdcells.v>:1203$2090.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'.

            
            Mapping `usb_rx_phy.$techmap$procmux$283.$and$<stdcells.v>:1203$2090.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'.

            
            Mapping `usb_rx_phy.$techmap$procmux$284_CMP0.$xor$<stdcells.v>:808$2083.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'.

            
            Mapping `usb_rx_phy.$techmap$procmux$284_CMP0.$xor$<stdcells.v>:808$2083.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=2\Y_WIDTH=2'.

            
            Mapping `usb_rx_phy.$techmap$procmux$533.$and$<stdcells.v>:1203$2095.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$533.$and$<stdcells.v>:1203$2095.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$533.$and$<stdcells.v>:1203$2096.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$533.$and$<stdcells.v>:1203$2096.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$533.$and$<stdcells.v>:1203$2097.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$533.$and$<stdcells.v>:1203$2097.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$569.$and$<stdcells.v>:1203$2101.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$569.$and$<stdcells.v>:1203$2101.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$569.$and$<stdcells.v>:1203$2102.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$569.$and$<stdcells.v>:1203$2102.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_rx_phy.$techmap$procmux$605.$and$<stdcells.v>:1203$2106.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$techmap$procmux$605.$and$<stdcells.v>:1203$2106.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$techmap$procmux$605.$and$<stdcells.v>:1203$2107.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$techmap$procmux$605.$and$<stdcells.v>:1203$2107.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$techmap$procmux$605.$and$<stdcells.v>:1203$2108.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$techmap$procmux$605.$and$<stdcells.v>:1203$2108.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$techmap$procmux$605.$and$<stdcells.v>:1203$2109.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$techmap$procmux$605.$and$<stdcells.v>:1203$2109.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$techmap$procmux$605.$and$<stdcells.v>:1203$2110.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$techmap$procmux$605.$and$<stdcells.v>:1203$2110.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$techmap$procmux$605.$and$<stdcells.v>:1203$2111.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$techmap$procmux$605.$and$<stdcells.v>:1203$2111.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$techmap$procmux$605.$and$<stdcells.v>:1203$2112.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_rx_phy.$techmap$procmux$605.$and$<stdcells.v>:1203$2112.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$add$rtl/usb_tx_phy.v:210$148.alu.V[0].adder' using `$fulladd'.

            
            Mapping `usb_tx_phy.$add$rtl/usb_tx_phy.v:210$148.alu.V[1].adder' using `$fulladd'.

            
            Mapping `usb_tx_phy.$add$rtl/usb_tx_phy.v:210$148.alu.V[2].adder' using `$fulladd'.

            
            Mapping `usb_tx_phy.$add$rtl/usb_tx_phy.v:261$165.alu.V[0].adder' using `$fulladd'.

            
            Mapping `usb_tx_phy.$add$rtl/usb_tx_phy.v:261$165.alu.V[1].adder' using `$fulladd'.

            
            Mapping `usb_tx_phy.$add$rtl/usb_tx_phy.v:261$165.alu.V[2].adder' using `$fulladd'.

            
            Mapping `usb_tx_phy.$techmap$eq$rtl/usb_tx_phy.v:229$153.$xor$<stdcells.v>:808$2078.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$eq$rtl/usb_tx_phy.v:229$153.$xor$<stdcells.v>:808$2078.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$eq$rtl/usb_tx_phy.v:264$166.$xor$<stdcells.v>:808$2078.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$eq$rtl/usb_tx_phy.v:264$166.$xor$<stdcells.v>:808$2078.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1363.$and$<stdcells.v>:1203$2118.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1363.$and$<stdcells.v>:1203$2118.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1363.$and$<stdcells.v>:1203$2119.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1363.$and$<stdcells.v>:1203$2119.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1363.$and$<stdcells.v>:1203$2120.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1363.$and$<stdcells.v>:1203$2120.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1363.$and$<stdcells.v>:1203$2121.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1363.$and$<stdcells.v>:1203$2121.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1363.$and$<stdcells.v>:1203$2122.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1363.$and$<stdcells.v>:1203$2122.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1363.$and$<stdcells.v>:1203$2123.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1363.$and$<stdcells.v>:1203$2123.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1363.$and$<stdcells.v>:1203$2124.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1363.$and$<stdcells.v>:1203$2124.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1364_CMP0.$xor$<stdcells.v>:808$2078.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1364_CMP0.$xor$<stdcells.v>:808$2078.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1366_CMP0.$xor$<stdcells.v>:808$2078.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1366_CMP0.$xor$<stdcells.v>:808$2078.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1368_CMP0.$xor$<stdcells.v>:808$2078.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1368_CMP0.$xor$<stdcells.v>:808$2078.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1370_CMP0.$xor$<stdcells.v>:808$2078.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1370_CMP0.$xor$<stdcells.v>:808$2078.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1372_CMP0.$xor$<stdcells.v>:808$2078.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1372_CMP0.$xor$<stdcells.v>:808$2078.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1374_CMP0.$xor$<stdcells.v>:808$2078.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1374_CMP0.$xor$<stdcells.v>:808$2078.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1376_CMP0.$xor$<stdcells.v>:808$2078.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1376_CMP0.$xor$<stdcells.v>:808$2078.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1592.$and$<stdcells.v>:1203$2101.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1592.$and$<stdcells.v>:1203$2101.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1592.$and$<stdcells.v>:1203$2102.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1592.$and$<stdcells.v>:1203$2102.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=1\Y_WIDTH=1'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1593_CMP0.$xor$<stdcells.v>:808$2078.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1593_CMP0.$xor$<stdcells.v>:808$2078.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1597_CMP0.$xor$<stdcells.v>:808$2078.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1597_CMP0.$xor$<stdcells.v>:808$2078.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1601_CMP0.$xor$<stdcells.v>:808$2078.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1601_CMP0.$xor$<stdcells.v>:808$2078.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1674.$and$<stdcells.v>:1203$2128.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1674.$and$<stdcells.v>:1203$2128.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1674.$and$<stdcells.v>:1203$2129.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1674.$and$<stdcells.v>:1203$2129.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1674.$and$<stdcells.v>:1203$2130.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1674.$and$<stdcells.v>:1203$2130.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1674.$and$<stdcells.v>:1203$2131.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1674.$and$<stdcells.v>:1203$2131.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1674.$and$<stdcells.v>:1203$2132.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1674.$and$<stdcells.v>:1203$2132.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1675_CMP0.$xor$<stdcells.v>:808$2078.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1675_CMP0.$xor$<stdcells.v>:808$2078.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1679_CMP0.$xor$<stdcells.v>:808$2078.A_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            Mapping `usb_tx_phy.$techmap$procmux$1679_CMP0.$xor$<stdcells.v>:808$2078.B_conv' using `$paramod$pos\A_SIGNED=0\A_WIDTH=3\Y_WIDTH=3'.

            
            No more expansions possible.


            11. Executing OPT pass (performing simple optimizations).


            11.1. Optimizing in-memory representation of design.


            11.2. Executing OPT_CONST pass (perform const folding).

            
            Replacing $_AND_ cell `$add$rtl/usb_phy.v:178$6.alu.V[0].adder.gate1' (?1) in module `\usb_phy' with constant driver `$add$rtl/usb_phy.v:178$6.alu.V[0].adder.t1 = $procdff$1980.Q [0]'.

            
            Replacing $_AND_ cell `$add$rtl/usb_phy.v:178$6.alu.V[0].adder.gate3' (?0) in module `\usb_phy' with constant driver `$add$rtl/usb_phy.v:178$6.alu.V[0].adder.t3 = 1'0'.

            
            Replacing $_XOR_ cell `$add$rtl/usb_phy.v:178$6.alu.V[0].adder.gate4' (?0) in module `\usb_phy' with constant driver `$add$rtl/usb_phy.v:178$6.alu.V[0].adder.Y = $add$rtl/usb_phy.v:178$6.alu.V[0].adder.t2'.

            
            Replacing $_AND_ cell `$add$rtl/usb_phy.v:178$6.alu.V[1].adder.gate1' (?0) in module `\usb_phy' with constant driver `$add$rtl/usb_phy.v:178$6.alu.V[1].adder.t1 = 1'0'.

            
            Replacing $_XOR_ cell `$add$rtl/usb_phy.v:178$6.alu.V[1].adder.gate2' (?0) in module `\usb_phy' with constant driver `$add$rtl/usb_phy.v:178$6.alu.V[1].adder.t2 = $procdff$1980.Q [1]'.

            
            Replacing $_AND_ cell `$add$rtl/usb_phy.v:178$6.alu.V[2].adder.gate1' (?0) in module `\usb_phy' with constant driver `$add$rtl/usb_phy.v:178$6.alu.V[2].adder.t1 = 1'0'.

            
            Replacing $_XOR_ cell `$add$rtl/usb_phy.v:178$6.alu.V[2].adder.gate2' (?0) in module `\usb_phy' with constant driver `$add$rtl/usb_phy.v:178$6.alu.V[2].adder.t2 = $procdff$1980.Q [2]'.

            
            Replacing $_AND_ cell `$add$rtl/usb_phy.v:178$6.alu.V[3].adder.gate1' (?0) in module `\usb_phy' with constant driver `$add$rtl/usb_phy.v:178$6.alu.V[3].adder.t1 = 1'0'.

            
            Replacing $_XOR_ cell `$add$rtl/usb_phy.v:178$6.alu.V[3].adder.gate2' (?0) in module `\usb_phy' with constant driver `$add$rtl/usb_phy.v:178$6.alu.V[3].adder.t2 = $procdff$1980.Q [3]'.

            
            Replacing $_AND_ cell `$add$rtl/usb_phy.v:178$6.alu.V[4].adder.gate1' (?0) in module `\usb_phy' with constant driver `$add$rtl/usb_phy.v:178$6.alu.V[4].adder.t1 = 1'0'.

            
            Replacing $_XOR_ cell `$add$rtl/usb_phy.v:178$6.alu.V[4].adder.gate2' (?0) in module `\usb_phy' with constant driver `$add$rtl/usb_phy.v:178$6.alu.V[4].adder.t2 = $procdff$1980.Q [4]'.

            
            Replacing $_XOR_ cell `$techmap$ne$rtl/usb_phy.v:176$3.$xor$<stdcells.v>:833$2076.V[0].gate' (?0) in module `\usb_phy' with constant driver `$techmap$ne$rtl/usb_phy.v:176$3.$xor$<stdcells.v>:833$2076.Y [0] = \LineState_o [0]'.

            
            Replacing $_XOR_ cell `$techmap$ne$rtl/usb_phy.v:176$3.$xor$<stdcells.v>:833$2076.V[1].gate' (?0) in module `\usb_phy' with constant driver `$techmap$ne$rtl/usb_phy.v:176$3.$xor$<stdcells.v>:833$2076.Y [1] = \LineState_o [1]'.

            
            Replacing $_OR_ cell `$add$rtl/usb_phy.v:178$6.alu.V[0].adder.gate5' (?0) in module `\usb_phy' with constant driver `$add$rtl/usb_phy.v:178$6.alu.V[0].adder.X = $procdff$1980.Q [0]'.

            
            Replacing $_OR_ cell `$add$rtl/usb_phy.v:178$6.alu.V[1].adder.gate5' (0?) in module `\usb_phy' with constant driver `$add$rtl/usb_phy.v:178$6.alu.V[1].adder.X = $add$rtl/usb_phy.v:178$6.alu.V[1].adder.t3'.

            
            Replacing $_OR_ cell `$add$rtl/usb_phy.v:178$6.alu.V[2].adder.gate5' (0?) in module `\usb_phy' with constant driver `$add$rtl/usb_phy.v:178$6.alu.V[2].adder.X = $add$rtl/usb_phy.v:178$6.alu.V[2].adder.t3'.

            
            Replacing $_OR_ cell `$add$rtl/usb_phy.v:178$6.alu.V[3].adder.gate5' (0?) in module `\usb_phy' with constant driver `$add$rtl/usb_phy.v:178$6.alu.V[3].adder.X = $add$rtl/usb_phy.v:178$6.alu.V[3].adder.t3'.

            
            Replacing $_OR_ cell `$add$rtl/usb_phy.v:178$6.alu.V[4].adder.gate5' (0?) in module `\usb_phy' with constant driver `$add$rtl/usb_phy.v:178$6.alu.V[4].adder.X = $add$rtl/usb_phy.v:178$6.alu.V[4].adder.t3'.

            
            Replacing $_AND_ cell `$add$rtl/usb_rx_phy.v:399$90.alu.V[0].adder.gate1' (?1) in module `\usb_rx_phy' with constant driver `$add$rtl/usb_rx_phy.v:399$90.alu.V[0].adder.t1 = $procdff$2006.Q [0]'.

            
            Replacing $_AND_ cell `$add$rtl/usb_rx_phy.v:399$90.alu.V[0].adder.gate3' (?0) in module `\usb_rx_phy' with constant driver `$add$rtl/usb_rx_phy.v:399$90.alu.V[0].adder.t3 = 1'0'.

            
            Replacing $_XOR_ cell `$add$rtl/usb_rx_phy.v:399$90.alu.V[0].adder.gate4' (?0) in module `\usb_rx_phy' with constant driver `$add$rtl/usb_rx_phy.v:399$90.alu.V[0].adder.Y = $add$rtl/usb_rx_phy.v:399$90.alu.V[0].adder.t2'.

            
            Replacing $_AND_ cell `$add$rtl/usb_rx_phy.v:399$90.alu.V[1].adder.gate1' (?0) in module `\usb_rx_phy' with constant driver `$add$rtl/usb_rx_phy.v:399$90.alu.V[1].adder.t1 = 1'0'.

            
            Replacing $_XOR_ cell `$add$rtl/usb_rx_phy.v:399$90.alu.V[1].adder.gate2' (?0) in module `\usb_rx_phy' with constant driver `$add$rtl/usb_rx_phy.v:399$90.alu.V[1].adder.t2 = $procdff$2006.Q [1]'.

            
            Replacing $_AND_ cell `$add$rtl/usb_rx_phy.v:399$90.alu.V[2].adder.gate1' (?0) in module `\usb_rx_phy' with constant driver `$add$rtl/usb_rx_phy.v:399$90.alu.V[2].adder.t1 = 1'0'.

            
            Replacing $_XOR_ cell `$add$rtl/usb_rx_phy.v:399$90.alu.V[2].adder.gate2' (?0) in module `\usb_rx_phy' with constant driver `$add$rtl/usb_rx_phy.v:399$90.alu.V[2].adder.t2 = $procdff$2006.Q [2]'.

            
            Replacing $_AND_ cell `$add$rtl/usb_rx_phy.v:432$109.alu.V[0].adder.gate1' (?1) in module `\usb_rx_phy' with constant driver `$add$rtl/usb_rx_phy.v:432$109.alu.V[0].adder.t1 = $procdff$2010.Q [0]'.

            
            Replacing $_AND_ cell `$add$rtl/usb_rx_phy.v:432$109.alu.V[0].adder.gate3' (?0) in module `\usb_rx_phy' with constant driver `$add$rtl/usb_rx_phy.v:432$109.alu.V[0].adder.t3 = 1'0'.

            
            Replacing $_XOR_ cell `$add$rtl/usb_rx_phy.v:432$109.alu.V[0].adder.gate4' (?0) in module `\usb_rx_phy' with constant driver `$add$rtl/usb_rx_phy.v:432$109.alu.V[0].adder.Y = $add$rtl/usb_rx_phy.v:432$109.alu.V[0].adder.t2'.

            
            Replacing $_AND_ cell `$add$rtl/usb_rx_phy.v:432$109.alu.V[1].adder.gate1' (?0) in module `\usb_rx_phy' with constant driver `$add$rtl/usb_rx_phy.v:432$109.alu.V[1].adder.t1 = 1'0'.

            
            Replacing $_XOR_ cell `$add$rtl/usb_rx_phy.v:432$109.alu.V[1].adder.gate2' (?0) in module `\usb_rx_phy' with constant driver `$add$rtl/usb_rx_phy.v:432$109.alu.V[1].adder.t2 = $procdff$2010.Q [1]'.

            
            Replacing $_AND_ cell `$add$rtl/usb_rx_phy.v:432$109.alu.V[2].adder.gate1' (?0) in module `\usb_rx_phy' with constant driver `$add$rtl/usb_rx_phy.v:432$109.alu.V[2].adder.t1 = 1'0'.

            
            Replacing $_XOR_ cell `$add$rtl/usb_rx_phy.v:432$109.alu.V[2].adder.gate2' (?0) in module `\usb_rx_phy' with constant driver `$add$rtl/usb_rx_phy.v:432$109.alu.V[2].adder.t2 = $procdff$2010.Q [2]'.

            
            Replacing $_MUX_ cell `$procmux$1016.V[0].gate' (00?) in module `\usb_rx_phy' with constant driver `$procmux$1016.Y [0] = 1'0'.

            
            Replacing $_MUX_ cell `$procmux$303.V[1].gate' (00?) in module `\usb_rx_phy' with constant driver `$procmux$303.Y [1] = 1'0'.

            
            Replacing $_MUX_ cell `$procmux$314.V[1].gate' (11?) in module `\usb_rx_phy' with constant driver `$procmux$314.Y [1] = 1'1'.

            
            Replacing $_MUX_ cell `$procmux$720.V[0].gate' (00?) in module `\usb_rx_phy' with constant driver `$procmux$720.Y [0] = 1'0'.

            
            Replacing $_MUX_ cell `$procmux$720.V[2].gate' (00?) in module `\usb_rx_phy' with constant driver `$procmux$720.Y [2] = 1'0'.

            
            Replacing $_MUX_ cell `$procmux$782.V[2].gate' (00?) in module `\usb_rx_phy' with constant driver `$procmux$782.Y [2] = 1'0'.

            
            Replacing $_MUX_ cell `$procmux$846.V[0].gate' (00?) in module `\usb_rx_phy' with constant driver `$procmux$846.Y [0] = 1'0'.

            
            Replacing $_MUX_ cell `$procmux$846.V[1].gate' (00?) in module `\usb_rx_phy' with constant driver `$procmux$846.Y [1] = 1'0'.

            
            Replacing $_MUX_ cell `$procmux$912.V[1].gate' (00?) in module `\usb_rx_phy' with constant driver `$procmux$912.Y [1] = 1'0'.

            
            Replacing $_XOR_ cell `$techmap$eq$rtl/usb_rx_phy.v:402$91.$xor$<stdcells.v>:808$2078.V[0].gate' (?0) in module `\usb_rx_phy' with constant driver `$techmap$eq$rtl/usb_rx_phy.v:402$91.$xor$<stdcells.v>:808$2078.Y [0] = $procdff$2006.Q [0]'.

            
            Replacing $_XOR_ cell `$techmap$procmux$1003_CMP0.$xor$<stdcells.v>:808$2078.V[0].gate' (?0) in module `\usb_rx_phy' with constant driver `$techmap$procmux$1003_CMP0.$xor$<stdcells.v>:808$2078.Y [0] = $procdff$2001.Q [0]'.

            
            Replacing $_XOR_ cell `$techmap$procmux$1003_CMP0.$xor$<stdcells.v>:808$2078.V[1].gate' (?0) in module `\usb_rx_phy' with constant driver `$techmap$procmux$1003_CMP0.$xor$<stdcells.v>:808$2078.Y [1] = $procdff$2001.Q [1]'.

            
            Replacing $_XOR_ cell `$techmap$procmux$1003_CMP0.$xor$<stdcells.v>:808$2078.V[2].gate' (?0) in module `\usb_rx_phy' with constant driver `$techmap$procmux$1003_CMP0.$xor$<stdcells.v>:808$2078.Y [2] = $procdff$2001.Q [2]'.

            
            Replacing $_XOR_ cell `$techmap$procmux$1019_CMP0.$xor$<stdcells.v>:808$2078.V[1].gate' (?0) in module `\usb_rx_phy' with constant driver `$techmap$procmux$1019_CMP0.$xor$<stdcells.v>:808$2078.Y [1] = $procdff$2001.Q [1]'.

            
            Replacing $_XOR_ cell `$techmap$procmux$1023_CMP0.$xor$<stdcells.v>:808$2078.V[0].gate' (?0) in module `\usb_rx_phy' with constant driver `$techmap$procmux$1023_CMP0.$xor$<stdcells.v>:808$2078.Y [0] = $procdff$2001.Q [0]'.

            
            Replacing $_XOR_ cell `$techmap$procmux$1023_CMP0.$xor$<stdcells.v>:808$2078.V[1].gate' (?0) in module `\usb_rx_phy' with constant driver `$techmap$procmux$1023_CMP0.$xor$<stdcells.v>:808$2078.Y [1] = $procdff$2001.Q [1]'.

            
            Replacing $_XOR_ cell `$techmap$procmux$1027_CMP0.$xor$<stdcells.v>:808$2078.V[2].gate' (?0) in module `\usb_rx_phy' with constant driver `$techmap$procmux$1027_CMP0.$xor$<stdcells.v>:808$2078.Y [2] = $procdff$2001.Q [2]'.

            
            Replacing $_XOR_ cell `$techmap$procmux$1031_CMP0.$xor$<stdcells.v>:808$2078.V[0].gate' (?0) in module `\usb_rx_phy' with constant driver `$techmap$procmux$1031_CMP0.$xor$<stdcells.v>:808$2078.Y [0] = $procdff$2001.Q [0]'.

            
            Replacing $_XOR_ cell `$techmap$procmux$1031_CMP0.$xor$<stdcells.v>:808$2078.V[2].gate' (?0) in module `\usb_rx_phy' with constant driver `$techmap$procmux$1031_CMP0.$xor$<stdcells.v>:808$2078.Y [2] = $procdff$2001.Q [2]'.

            
            Replacing $_XOR_ cell `$techmap$procmux$1035_CMP0.$xor$<stdcells.v>:808$2078.V[1].gate' (?0) in module `\usb_rx_phy' with constant driver `$techmap$procmux$1035_CMP0.$xor$<stdcells.v>:808$2078.Y [1] = $procdff$2001.Q [1]'.

            
            Replacing $_XOR_ cell `$techmap$procmux$1035_CMP0.$xor$<stdcells.v>:808$2078.V[2].gate' (?0) in module `\usb_rx_phy' with constant driver `$techmap$procmux$1035_CMP0.$xor$<stdcells.v>:808$2078.Y [2] = $procdff$2001.Q [2]'.

            
            Replacing $_XOR_ cell `$techmap$procmux$1160_CMP0.$xor$<stdcells.v>:808$2078.V[0].gate' (?0) in module `\usb_rx_phy' with constant driver `$techmap$procmux$1160_CMP0.$xor$<stdcells.v>:808$2078.Y [0] = $procdff$2001.Q [0]'.

            
            Replacing $_XOR_ cell `$techmap$procmux$273_CMP0.$xor$<stdcells.v>:808$2083.V[1].gate' (?0) in module `\usb_rx_phy' with constant driver `$techmap$procmux$273_CMP0.$xor$<stdcells.v>:808$2083.Y [1] = $procdff$1997.Q [1]'.

            
            Replacing $_XOR_ cell `$techmap$procmux$277_CMP0.$xor$<stdcells.v>:808$2083.V[0].gate' (?0) in module `\usb_rx_phy' with constant driver `$techmap$procmux$277_CMP0.$xor$<stdcells.v>:808$2083.Y [0] = $procdff$1997.Q [0]'.

            
            Replacing $_XOR_ cell `$techmap$procmux$277_CMP0.$xor$<stdcells.v>:808$2083.V[1].gate' (?0) in module `\usb_rx_phy' with constant driver `$techmap$procmux$277_CMP0.$xor$<stdcells.v>:808$2083.Y [1] = $procdff$1997.Q [1]'.

            
            Replacing $_XOR_ cell `$techmap$procmux$284_CMP0.$xor$<stdcells.v>:808$2083.V[0].gate' (?0) in module `\usb_rx_phy' with constant driver `$techmap$procmux$284_CMP0.$xor$<stdcells.v>:808$2083.Y [0] = $procdff$1997.Q [0]'.

            
            Replacing $_AND_ cell `$techmap$procmux$569.$and$<stdcells.v>:1203$2101.V[0].gate' (0?) in module `\usb_rx_phy' with constant driver `$techmap$procmux$569.$and$<stdcells.v>:1203$2101.Y = 1'0'.

            
            Replacing $_OR_ cell `$add$rtl/usb_rx_phy.v:399$90.alu.V[0].adder.gate5' (?0) in module `\usb_rx_phy' with constant driver `$add$rtl/usb_rx_phy.v:399$90.alu.V[0].adder.X = $procdff$2006.Q [0]'.

            
            Replacing $_OR_ cell `$add$rtl/usb_rx_phy.v:399$90.alu.V[1].adder.gate5' (0?) in module `\usb_rx_phy' with constant driver `$add$rtl/usb_rx_phy.v:399$90.alu.V[1].adder.X = $add$rtl/usb_rx_phy.v:399$90.alu.V[1].adder.t3'.

            
            Replacing $_OR_ cell `$add$rtl/usb_rx_phy.v:399$90.alu.V[2].adder.gate5' (0?) in module `\usb_rx_phy' with constant driver `$add$rtl/usb_rx_phy.v:399$90.alu.V[2].adder.X = $add$rtl/usb_rx_phy.v:399$90.alu.V[2].adder.t3'.

            
            Replacing $_OR_ cell `$add$rtl/usb_rx_phy.v:432$109.alu.V[0].adder.gate5' (?0) in module `\usb_rx_phy' with constant driver `$add$rtl/usb_rx_phy.v:432$109.alu.V[0].adder.X = $procdff$2010.Q [0]'.

            
            Replacing $_OR_ cell `$add$rtl/usb_rx_phy.v:432$109.alu.V[1].adder.gate5' (0?) in module `\usb_rx_phy' with constant driver `$add$rtl/usb_rx_phy.v:432$109.alu.V[1].adder.X = $add$rtl/usb_rx_phy.v:432$109.alu.V[1].adder.t3'.

            
            Replacing $_OR_ cell `$add$rtl/usb_rx_phy.v:432$109.alu.V[2].adder.gate5' (0?) in module `\usb_rx_phy' with constant driver `$add$rtl/usb_rx_phy.v:432$109.alu.V[2].adder.X = $add$rtl/usb_rx_phy.v:432$109.alu.V[2].adder.t3'.

            
            Replacing $_AND_ cell `$techmap$procmux$283.$and$<stdcells.v>:1203$2089.V[1].gate' (1?) in module `\usb_rx_phy' with constant driver `$techmap$procmux$283.$and$<stdcells.v>:1203$2089.Y [1] = $techmap$procmux$273_CMP0.$not$<stdcells.v>:808$2085.Y'.

            
            Replacing $_AND_ cell `$techmap$procmux$283.$and$<stdcells.v>:1203$2090.V[1].gate' (0?) in module `\usb_rx_phy' with constant driver `$techmap$procmux$283.$and$<stdcells.v>:1203$2090.Y [1] = 1'0'.

            
            Replacing $_OR_ cell `$techmap$procmux$569.$reduce_or$<stdcells.v>:1210$2103.V[1].gate' (?0) in module `\usb_rx_phy' with constant driver `$techmap$procmux$569.$reduce_or$<stdcells.v>:1210$2103.buffer [1] = $techmap$procmux$569.$and$<stdcells.v>:1203$2102.Y'.

            
            Replacing $_AND_ cell `$techmap$procmux$605.$and$<stdcells.v>:1203$2107.V[0].gate' (0?) in module `\usb_rx_phy' with constant driver `$techmap$procmux$605.$and$<stdcells.v>:1203$2107.Y [0] = 1'0'.

            
            Replacing $_AND_ cell `$techmap$procmux$605.$and$<stdcells.v>:1203$2108.V[1].gate' (0?) in module `\usb_rx_phy' with constant driver `$techmap$procmux$605.$and$<stdcells.v>:1203$2108.Y [1] = 1'0'.

            
            Replacing $_AND_ cell `$techmap$procmux$605.$and$<stdcells.v>:1203$2109.V[0].gate' (0?) in module `\usb_rx_phy' with constant driver `$techmap$procmux$605.$and$<stdcells.v>:1203$2109.Y [0] = 1'0'.

            
            Replacing $_AND_ cell `$techmap$procmux$605.$and$<stdcells.v>:1203$2109.V[1].gate' (0?) in module `\usb_rx_phy' with constant driver `$techmap$procmux$605.$and$<stdcells.v>:1203$2109.Y [1] = 1'0'.

            
            Replacing $_AND_ cell `$techmap$procmux$605.$and$<stdcells.v>:1203$2110.V[2].gate' (0?) in module `\usb_rx_phy' with constant driver `$techmap$procmux$605.$and$<stdcells.v>:1203$2110.Y [2] = 1'0'.

            
            Replacing $_AND_ cell `$techmap$procmux$605.$and$<stdcells.v>:1203$2111.V[0].gate' (0?) in module `\usb_rx_phy' with constant driver `$techmap$procmux$605.$and$<stdcells.v>:1203$2111.Y [0] = 1'0'.

            
            Replacing $_AND_ cell `$techmap$procmux$605.$and$<stdcells.v>:1203$2111.V[2].gate' (0?) in module `\usb_rx_phy' with constant driver `$techmap$procmux$605.$and$<stdcells.v>:1203$2111.Y [2] = 1'0'.

            
            Replacing $_OR_ cell `$techmap$procmux$283.$reduce_or$<stdcells.v>:1210$2092.V[2].gate' (0?) in module `\usb_rx_phy' with constant driver `$techmap$procmux$283.$reduce_or$<stdcells.v>:1210$2092.buffer [2] = $techmap$procmux$283.$reduce_or$<stdcells.v>:1210$2092.buffer [1]'.

            
            Replacing $_OR_ cell `$techmap$procmux$605.$reduce_or$<stdcells.v>:1210$2113.V[1].gate' (0?) in module `\usb_rx_phy' with constant driver `$techmap$procmux$605.$reduce_or$<stdcells.v>:1210$2113.buffer [1] = $techmap$procmux$605.$and$<stdcells.v>:1203$2106.Y [0]'.

            
            Replacing $_OR_ cell `$techmap$procmux$605.$reduce_or$<stdcells.v>:1210$2113.V[3].gate' (0?) in module `\usb_rx_phy' with constant driver `$techmap$procmux$605.$reduce_or$<stdcells.v>:1210$2113.buffer [3] = $techmap$procmux$605.$reduce_or$<stdcells.v>:1210$2113.buffer [2]'.

            
            Replacing $_OR_ cell `$techmap$procmux$605.$reduce_or$<stdcells.v>:1210$2113.V[5].gate' (0?) in module `\usb_rx_phy' with constant driver `$techmap$procmux$605.$reduce_or$<stdcells.v>:1210$2113.buffer [5] = $techmap$procmux$605.$reduce_or$<stdcells.v>:1210$2113.buffer [4]'.

            
            Replacing $_OR_ cell `$techmap$procmux$605.$reduce_or$<stdcells.v>:1210$2114.V[2].gate' (0?) in module `\usb_rx_phy' with constant driver `$techmap$procmux$605.$reduce_or$<stdcells.v>:1210$2114.buffer [2] = $techmap$procmux$605.$reduce_or$<stdcells.v>:1210$2114.buffer [1]'.

            
            Replacing $_OR_ cell `$techmap$procmux$605.$reduce_or$<stdcells.v>:1210$2114.V[3].gate' (0?) in module `\usb_rx_phy' with constant driver `$techmap$procmux$605.$reduce_or$<stdcells.v>:1210$2114.buffer [3] = $techmap$procmux$605.$reduce_or$<stdcells.v>:1210$2114.buffer [2]'.

            
            Replacing $_OR_ cell `$techmap$procmux$605.$reduce_or$<stdcells.v>:1210$2115.V[4].gate' (0?) in module `\usb_rx_phy' with constant driver `$techmap$procmux$605.$reduce_or$<stdcells.v>:1210$2115.buffer [4] = $techmap$procmux$605.$reduce_or$<stdcells.v>:1210$2115.buffer [3]'.

            
            Replacing $_OR_ cell `$techmap$procmux$605.$reduce_or$<stdcells.v>:1210$2115.V[5].gate' (0?) in module `\usb_rx_phy' with constant driver `$techmap$procmux$605.$reduce_or$<stdcells.v>:1210$2115.buffer [5] = $techmap$procmux$605.$reduce_or$<stdcells.v>:1210$2115.buffer [4]'.

            
            Replacing $_AND_ cell `$add$rtl/usb_tx_phy.v:210$148.alu.V[0].adder.gate1' (?1) in module `\usb_tx_phy' with constant driver `$add$rtl/usb_tx_phy.v:210$148.alu.V[0].adder.t1 = $procdff$2020.Q [0]'.

            
            Replacing $_AND_ cell `$add$rtl/usb_tx_phy.v:210$148.alu.V[0].adder.gate3' (?0) in module `\usb_tx_phy' with constant driver `$add$rtl/usb_tx_phy.v:210$148.alu.V[0].adder.t3 = 1'0'.

            
            Replacing $_XOR_ cell `$add$rtl/usb_tx_phy.v:210$148.alu.V[0].adder.gate4' (?0) in module `\usb_tx_phy' with constant driver `$add$rtl/usb_tx_phy.v:210$148.alu.V[0].adder.Y = $add$rtl/usb_tx_phy.v:210$148.alu.V[0].adder.t2'.

            
            Replacing $_AND_ cell `$add$rtl/usb_tx_phy.v:210$148.alu.V[1].adder.gate1' (?0) in module `\usb_tx_phy' with constant driver `$add$rtl/usb_tx_phy.v:210$148.alu.V[1].adder.t1 = 1'0'.

            
            Replacing $_XOR_ cell `$add$rtl/usb_tx_phy.v:210$148.alu.V[1].adder.gate2' (?0) in module `\usb_tx_phy' with constant driver `$add$rtl/usb_tx_phy.v:210$148.alu.V[1].adder.t2 = $procdff$2020.Q [1]'.

            
            Replacing $_AND_ cell `$add$rtl/usb_tx_phy.v:210$148.alu.V[2].adder.gate1' (?0) in module `\usb_tx_phy' with constant driver `$add$rtl/usb_tx_phy.v:210$148.alu.V[2].adder.t1 = 1'0'.

            
            Replacing $_XOR_ cell `$add$rtl/usb_tx_phy.v:210$148.alu.V[2].adder.gate2' (?0) in module `\usb_tx_phy' with constant driver `$add$rtl/usb_tx_phy.v:210$148.alu.V[2].adder.t2 = $procdff$2020.Q [2]'.

            
            Replacing $_AND_ cell `$add$rtl/usb_tx_phy.v:261$165.alu.V[0].adder.gate1' (?1) in module `\usb_tx_phy' with constant driver `$add$rtl/usb_tx_phy.v:261$165.alu.V[0].adder.t1 = $procdff$2026.Q [0]'.

            
            Replacing $_AND_ cell `$add$rtl/usb_tx_phy.v:261$165.alu.V[0].adder.gate3' (?0) in module `\usb_tx_phy' with constant driver `$add$rtl/usb_tx_phy.v:261$165.alu.V[0].adder.t3 = 1'0'.

            
            Replacing $_XOR_ cell `$add$rtl/usb_tx_phy.v:261$165.alu.V[0].adder.gate4' (?0) in module `\usb_tx_phy' with constant driver `$add$rtl/usb_tx_phy.v:261$165.alu.V[0].adder.Y = $add$rtl/usb_tx_phy.v:261$165.alu.V[0].adder.t2'.

            
            Replacing $_AND_ cell `$add$rtl/usb_tx_phy.v:261$165.alu.V[1].adder.gate1' (?0) in module `\usb_tx_phy' with constant driver `$add$rtl/usb_tx_phy.v:261$165.alu.V[1].adder.t1 = 1'0'.

            
            Replacing $_XOR_ cell `$add$rtl/usb_tx_phy.v:261$165.alu.V[1].adder.gate2' (?0) in module `\usb_tx_phy' with constant driver `$add$rtl/usb_tx_phy.v:261$165.alu.V[1].adder.t2 = $procdff$2026.Q [1]'.

            
            Replacing $_AND_ cell `$add$rtl/usb_tx_phy.v:261$165.alu.V[2].adder.gate1' (?0) in module `\usb_tx_phy' with constant driver `$add$rtl/usb_tx_phy.v:261$165.alu.V[2].adder.t1 = 1'0'.

            
            Replacing $_XOR_ cell `$add$rtl/usb_tx_phy.v:261$165.alu.V[2].adder.gate2' (?0) in module `\usb_tx_phy' with constant driver `$add$rtl/usb_tx_phy.v:261$165.alu.V[2].adder.t2 = $procdff$2026.Q [2]'.

            
            Replacing $_XOR_ cell `$techmap$eq$rtl/usb_tx_phy.v:264$166.$xor$<stdcells.v>:808$2078.V[0].gate' (?0) in module `\usb_tx_phy' with constant driver `$techmap$eq$rtl/usb_tx_phy.v:264$166.$xor$<stdcells.v>:808$2078.Y [0] = $procdff$2026.Q [0]'.

            
            Replacing $_XOR_ cell `$techmap$procmux$1364_CMP0.$xor$<stdcells.v>:808$2078.V[0].gate' (?0) in module `\usb_tx_phy' with constant driver `$techmap$procmux$1364_CMP0.$xor$<stdcells.v>:808$2078.Y [0] = $procdff$2020.Q [0]'.

            
            Replacing $_XOR_ cell `$techmap$procmux$1366_CMP0.$xor$<stdcells.v>:808$2078.V[1].gate' (?0) in module `\usb_tx_phy' with constant driver `$techmap$procmux$1366_CMP0.$xor$<stdcells.v>:808$2078.Y [1] = $procdff$2020.Q [1]'.

            
            Replacing $_XOR_ cell `$techmap$procmux$1368_CMP0.$xor$<stdcells.v>:808$2078.V[0].gate' (?0) in module `\usb_tx_phy' with constant driver `$techmap$procmux$1368_CMP0.$xor$<stdcells.v>:808$2078.Y [0] = $procdff$2020.Q [0]'.

            
            Replacing $_XOR_ cell `$techmap$procmux$1368_CMP0.$xor$<stdcells.v>:808$2078.V[1].gate' (?0) in module `\usb_tx_phy' with constant driver `$techmap$procmux$1368_CMP0.$xor$<stdcells.v>:808$2078.Y [1] = $procdff$2020.Q [1]'.

            
            Replacing $_XOR_ cell `$techmap$procmux$1370_CMP0.$xor$<stdcells.v>:808$2078.V[2].gate' (?0) in module `\usb_tx_phy' with constant driver `$techmap$procmux$1370_CMP0.$xor$<stdcells.v>:808$2078.Y [2] = $procdff$2020.Q [2]'.

            
            Replacing $_XOR_ cell `$techmap$procmux$1372_CMP0.$xor$<stdcells.v>:808$2078.V[0].gate' (?0) in module `\usb_tx_phy' with constant driver `$techmap$procmux$1372_CMP0.$xor$<stdcells.v>:808$2078.Y [0] = $procdff$2020.Q [0]'.

            
            Replacing $_XOR_ cell `$techmap$procmux$1372_CMP0.$xor$<stdcells.v>:808$2078.V[2].gate' (?0) in module `\usb_tx_phy' with constant driver `$techmap$procmux$1372_CMP0.$xor$<stdcells.v>:808$2078.Y [2] = $procdff$2020.Q [2]'.

            
            Replacing $_XOR_ cell `$techmap$procmux$1374_CMP0.$xor$<stdcells.v>:808$2078.V[1].gate' (?0) in module `\usb_tx_phy' with constant driver `$techmap$procmux$1374_CMP0.$xor$<stdcells.v>:808$2078.Y [1] = $procdff$2020.Q [1]'.

            
            Replacing $_XOR_ cell `$techmap$procmux$1374_CMP0.$xor$<stdcells.v>:808$2078.V[2].gate' (?0) in module `\usb_tx_phy' with constant driver `$techmap$procmux$1374_CMP0.$xor$<stdcells.v>:808$2078.Y [2] = $procdff$2020.Q [2]'.

            
            Replacing $_XOR_ cell `$techmap$procmux$1376_CMP0.$xor$<stdcells.v>:808$2078.V[0].gate' (?0) in module `\usb_tx_phy' with constant driver `$techmap$procmux$1376_CMP0.$xor$<stdcells.v>:808$2078.Y [0] = $procdff$2020.Q [0]'.

            
            Replacing $_XOR_ cell `$techmap$procmux$1376_CMP0.$xor$<stdcells.v>:808$2078.V[1].gate' (?0) in module `\usb_tx_phy' with constant driver `$techmap$procmux$1376_CMP0.$xor$<stdcells.v>:808$2078.Y [1] = $procdff$2020.Q [1]'.

            
            Replacing $_XOR_ cell `$techmap$procmux$1376_CMP0.$xor$<stdcells.v>:808$2078.V[2].gate' (?0) in module `\usb_tx_phy' with constant driver `$techmap$procmux$1376_CMP0.$xor$<stdcells.v>:808$2078.Y [2] = $procdff$2020.Q [2]'.

            
            Replacing $_XOR_ cell `$techmap$procmux$1593_CMP0.$xor$<stdcells.v>:808$2078.V[0].gate' (?0) in module `\usb_tx_phy' with constant driver `$techmap$procmux$1593_CMP0.$xor$<stdcells.v>:808$2078.Y [0] = $procdff$2039.Q [0]'.

            
            Replacing $_XOR_ cell `$techmap$procmux$1593_CMP0.$xor$<stdcells.v>:808$2078.V[2].gate' (?0) in module `\usb_tx_phy' with constant driver `$techmap$procmux$1593_CMP0.$xor$<stdcells.v>:808$2078.Y [2] = $procdff$2039.Q [2]'.

            
            Replacing $_XOR_ cell `$techmap$procmux$1597_CMP0.$xor$<stdcells.v>:808$2078.V[1].gate' (?0) in module `\usb_tx_phy' with constant driver `$techmap$procmux$1597_CMP0.$xor$<stdcells.v>:808$2078.Y [1] = $procdff$2039.Q [1]'.

            
            Replacing $_XOR_ cell `$techmap$procmux$1597_CMP0.$xor$<stdcells.v>:808$2078.V[2].gate' (?0) in module `\usb_tx_phy' with constant driver `$techmap$procmux$1597_CMP0.$xor$<stdcells.v>:808$2078.Y [2] = $procdff$2039.Q [2]'.

            
            Replacing $_XOR_ cell `$techmap$procmux$1601_CMP0.$xor$<stdcells.v>:808$2078.V[0].gate' (?0) in module `\usb_tx_phy' with constant driver `$techmap$procmux$1601_CMP0.$xor$<stdcells.v>:808$2078.Y [0] = $procdff$2039.Q [0]'.

            
            Replacing $_XOR_ cell `$techmap$procmux$1601_CMP0.$xor$<stdcells.v>:808$2078.V[1].gate' (?0) in module `\usb_tx_phy' with constant driver `$techmap$procmux$1601_CMP0.$xor$<stdcells.v>:808$2078.Y [1] = $procdff$2039.Q [1]'.

            
            Replacing $_XOR_ cell `$techmap$procmux$1601_CMP0.$xor$<stdcells.v>:808$2078.V[2].gate' (?0) in module `\usb_tx_phy' with constant driver `$techmap$procmux$1601_CMP0.$xor$<stdcells.v>:808$2078.Y [2] = $procdff$2039.Q [2]'.

            
            Replacing $_XOR_ cell `$techmap$procmux$1675_CMP0.$xor$<stdcells.v>:808$2078.V[0].gate' (?0) in module `\usb_tx_phy' with constant driver `$techmap$procmux$1675_CMP0.$xor$<stdcells.v>:808$2078.Y [0] = $procdff$2039.Q [0]'.

            
            Replacing $_XOR_ cell `$techmap$procmux$1675_CMP0.$xor$<stdcells.v>:808$2078.V[1].gate' (?0) in module `\usb_tx_phy' with constant driver `$techmap$procmux$1675_CMP0.$xor$<stdcells.v>:808$2078.Y [1] = $procdff$2039.Q [1]'.

            
            Replacing $_XOR_ cell `$techmap$procmux$1679_CMP0.$xor$<stdcells.v>:808$2078.V[2].gate' (?0) in module `\usb_tx_phy' with constant driver `$techmap$procmux$1679_CMP0.$xor$<stdcells.v>:808$2078.Y [2] = $procdff$2039.Q [2]'.

            
            Replacing $_OR_ cell `$add$rtl/usb_tx_phy.v:210$148.alu.V[0].adder.gate5' (?0) in module `\usb_tx_phy' with constant driver `$add$rtl/usb_tx_phy.v:210$148.alu.V[0].adder.X = $procdff$2020.Q [0]'.

            
            Replacing $_OR_ cell `$add$rtl/usb_tx_phy.v:210$148.alu.V[1].adder.gate5' (0?) in module `\usb_tx_phy' with constant driver `$add$rtl/usb_tx_phy.v:210$148.alu.V[1].adder.X = $add$rtl/usb_tx_phy.v:210$148.alu.V[1].adder.t3'.

            
            Replacing $_OR_ cell `$add$rtl/usb_tx_phy.v:210$148.alu.V[2].adder.gate5' (0?) in module `\usb_tx_phy' with constant driver `$add$rtl/usb_tx_phy.v:210$148.alu.V[2].adder.X = $add$rtl/usb_tx_phy.v:210$148.alu.V[2].adder.t3'.

            
            Replacing $_OR_ cell `$add$rtl/usb_tx_phy.v:261$165.alu.V[0].adder.gate5' (?0) in module `\usb_tx_phy' with constant driver `$add$rtl/usb_tx_phy.v:261$165.alu.V[0].adder.X = $procdff$2026.Q [0]'.

            
            Replacing $_OR_ cell `$add$rtl/usb_tx_phy.v:261$165.alu.V[1].adder.gate5' (0?) in module `\usb_tx_phy' with constant driver `$add$rtl/usb_tx_phy.v:261$165.alu.V[1].adder.X = $add$rtl/usb_tx_phy.v:261$165.alu.V[1].adder.t3'.

            
            Replacing $_OR_ cell `$add$rtl/usb_tx_phy.v:261$165.alu.V[2].adder.gate5' (0?) in module `\usb_tx_phy' with constant driver `$add$rtl/usb_tx_phy.v:261$165.alu.V[2].adder.X = $add$rtl/usb_tx_phy.v:261$165.alu.V[2].adder.t3'.


            11.3. Executing OPT_SHARE pass (detect identical cells).

            
            Full command line: opt_share -nomux

            
            Finding identical cells in module `\usb_phy'.

            
              Cell `$techmap$eq$rtl/usb_phy.v:181$8.$xor$<stdcells.v>:808$2073.V[0].gate' is identical to cell `$add$rtl/usb_phy.v:178$6.alu.V[0].adder.gate2'.

            
                Redirecting output \Y: $techmap$eq$rtl/usb_phy.v:181$8.$xor$<stdcells.v>:808$2073.Y [0] = $add$rtl/usb_phy.v:178$6.alu.V[0].adder.t2

            
                Removing $_XOR_ cell `$techmap$eq$rtl/usb_phy.v:181$8.$xor$<stdcells.v>:808$2073.V[0].gate' from module `\usb_phy'.

            
            Finding identical cells in module `\usb_rx_phy'.

            
              Cell `$procmux$1016.V[2].gate' is identical to cell `$procmux$1016.V[1].gate'.

            
                Redirecting output \Y: $procmux$1016.Y [2] = $procmux$1016.Y [1]

            
                Removing $_MUX_ cell `$procmux$1016.V[2].gate' from module `\usb_rx_phy'.

            
              Cell `$procmux$1194.V[0].gate' is identical to cell `$procmux$1123.V[0].gate'.

            
                Redirecting output \Y: $procmux$1194.Y [0] = $procmux$1123.Y

            
                Removing $_MUX_ cell `$procmux$1194.V[0].gate' from module `\usb_rx_phy'.

            
              Cell `$procmux$1194.V[1].gate' is identical to cell `$procmux$1123.V[0].gate'.

            
                Redirecting output \Y: $procmux$1194.Y [1] = $procmux$1123.Y

            
                Removing $_MUX_ cell `$procmux$1194.V[1].gate' from module `\usb_rx_phy'.

            
              Cell `$procmux$1194.V[2].gate' is identical to cell `$procmux$1123.V[0].gate'.

            
                Redirecting output \Y: $procmux$1194.Y [2] = $procmux$1123.Y

            
                Removing $_MUX_ cell `$procmux$1194.V[2].gate' from module `\usb_rx_phy'.

            
              Cell `$procmux$326.V[0].gate' is identical to cell `$procmux$303.V[0].gate'.

            
                Redirecting output \Y: $procmux$326.Y [0] = $procmux$303.Y [0]

            
                Removing $_MUX_ cell `$procmux$326.V[0].gate' from module `\usb_rx_phy'.

            
              Cell `$procmux$326.V[1].gate' is identical to cell `$procmux$303.V[0].gate'.

            
                Redirecting output \Y: $procmux$326.Y [1] = $procmux$303.Y [0]

            
                Removing $_MUX_ cell `$procmux$326.V[1].gate' from module `\usb_rx_phy'.

            
              Cell `$procmux$720.V[1].gate' is identical to cell `$procmux$1016.V[1].gate'.

            
                Redirecting output \Y: $procmux$720.Y [1] = $procmux$1016.Y [1]

            
                Removing $_MUX_ cell `$procmux$720.V[1].gate' from module `\usb_rx_phy'.

            
              Cell `$procmux$782.V[0].gate' is identical to cell `$procmux$1123.V[0].gate'.

            
                Redirecting output \Y: $procmux$782.Y [0] = $procmux$1123.Y

            
                Removing $_MUX_ cell `$procmux$782.V[0].gate' from module `\usb_rx_phy'.

            
              Cell `$procmux$782.V[1].gate' is identical to cell `$procmux$1123.V[0].gate'.

            
                Redirecting output \Y: $procmux$782.Y [1] = $procmux$1123.Y

            
                Removing $_MUX_ cell `$procmux$782.V[1].gate' from module `\usb_rx_phy'.

            
              Cell `$procmux$846.V[2].gate' is identical to cell `$procmux$1016.V[1].gate'.

            
                Redirecting output \Y: $procmux$846.Y [2] = $procmux$1016.Y [1]

            
                Removing $_MUX_ cell `$procmux$846.V[2].gate' from module `\usb_rx_phy'.

            
              Cell `$procmux$912.V[0].gate' is identical to cell `$procmux$1123.V[0].gate'.

            
                Redirecting output \Y: $procmux$912.Y [0] = $procmux$1123.Y

            
                Removing $_MUX_ cell `$procmux$912.V[0].gate' from module `\usb_rx_phy'.

            
              Cell `$procmux$912.V[2].gate' is identical to cell `$procmux$1123.V[0].gate'.

            
                Redirecting output \Y: $procmux$912.Y [2] = $procmux$1123.Y

            
                Removing $_MUX_ cell `$procmux$912.V[2].gate' from module `\usb_rx_phy'.

            
              Cell `$techmap$eq$rtl/usb_rx_phy.v:441$114.$xor$<stdcells.v>:808$2078.V[0].gate' is identical to cell `$add$rtl/usb_rx_phy.v:432$109.alu.V[0].adder.gate2'.

            
                Redirecting output \Y: $techmap$eq$rtl/usb_rx_phy.v:441$114.$xor$<stdcells.v>:808$2078.Y [0] = $add$rtl/usb_rx_phy.v:432$109.alu.V[0].adder.t2

            
                Removing $_XOR_ cell `$techmap$eq$rtl/usb_rx_phy.v:441$114.$xor$<stdcells.v>:808$2078.V[0].gate' from module `\usb_rx_phy'.

            
              Cell `$techmap$procmux$1023_CMP0.$reduce_or$<stdcells.v>:808$2079.V[1].gate' is identical to cell `$techmap$procmux$1003_CMP0.$reduce_or$<stdcells.v>:808$2079.V[1].gate'.

            
                Redirecting output \Y: $techmap$procmux$1023_CMP0.$reduce_or$<stdcells.v>:808$2079.buffer [1] = $techmap$procmux$1003_CMP0.$reduce_or$<stdcells.v>:808$2079.buffer [1]

            
                Removing $_OR_ cell `$techmap$procmux$1023_CMP0.$reduce_or$<stdcells.v>:808$2079.V[1].gate' from module `\usb_rx_phy'.

            
              Cell `$techmap$procmux$1023_CMP0.$xor$<stdcells.v>:808$2078.V[2].gate' is identical to cell `$techmap$procmux$1019_CMP0.$xor$<stdcells.v>:808$2078.V[2].gate'.

            
                Redirecting output \Y: $techmap$procmux$1023_CMP0.$xor$<stdcells.v>:808$2078.Y [2] = $techmap$procmux$1019_CMP0.$xor$<stdcells.v>:808$2078.Y [2]

            
                Removing $_XOR_ cell `$techmap$procmux$1023_CMP0.$xor$<stdcells.v>:808$2078.V[2].gate' from module `\usb_rx_phy'.

            
              Cell `$techmap$procmux$1027_CMP0.$xor$<stdcells.v>:808$2078.V[0].gate' is identical to cell `$techmap$procmux$1019_CMP0.$xor$<stdcells.v>:808$2078.V[0].gate'.

            
                Redirecting output \Y: $techmap$procmux$1027_CMP0.$xor$<stdcells.v>:808$2078.Y [0] = $techmap$procmux$1019_CMP0.$xor$<stdcells.v>:808$2078.Y [0]

            
                Removing $_XOR_ cell `$techmap$procmux$1027_CMP0.$xor$<stdcells.v>:808$2078.V[0].gate' from module `\usb_rx_phy'.

            
              Cell `$techmap$procmux$1031_CMP0.$xor$<stdcells.v>:808$2078.V[1].gate' is identical to cell `$techmap$procmux$1027_CMP0.$xor$<stdcells.v>:808$2078.V[1].gate'.

            
                Redirecting output \Y: $techmap$procmux$1031_CMP0.$xor$<stdcells.v>:808$2078.Y [1] = $techmap$procmux$1027_CMP0.$xor$<stdcells.v>:808$2078.Y [1]

            
                Removing $_XOR_ cell `$techmap$procmux$1031_CMP0.$xor$<stdcells.v>:808$2078.V[1].gate' from module `\usb_rx_phy'.

            
              Cell `$techmap$procmux$1035_CMP0.$xor$<stdcells.v>:808$2078.V[0].gate' is identical to cell `$techmap$procmux$1019_CMP0.$xor$<stdcells.v>:808$2078.V[0].gate'.

            
                Redirecting output \Y: $techmap$procmux$1035_CMP0.$xor$<stdcells.v>:808$2078.Y [0] = $techmap$procmux$1019_CMP0.$xor$<stdcells.v>:808$2078.Y [0]

            
                Removing $_XOR_ cell `$techmap$procmux$1035_CMP0.$xor$<stdcells.v>:808$2078.V[0].gate' from module `\usb_rx_phy'.

            
              Cell `$techmap$procmux$1160_CMP0.$xor$<stdcells.v>:808$2078.V[1].gate' is identical to cell `$techmap$procmux$1027_CMP0.$xor$<stdcells.v>:808$2078.V[1].gate'.

            
                Redirecting output \Y: $techmap$procmux$1160_CMP0.$xor$<stdcells.v>:808$2078.Y [1] = $techmap$procmux$1027_CMP0.$xor$<stdcells.v>:808$2078.Y [1]

            
                Removing $_XOR_ cell `$techmap$procmux$1160_CMP0.$xor$<stdcells.v>:808$2078.V[1].gate' from module `\usb_rx_phy'.

            
              Cell `$techmap$procmux$1160_CMP0.$xor$<stdcells.v>:808$2078.V[2].gate' is identical to cell `$techmap$procmux$1019_CMP0.$xor$<stdcells.v>:808$2078.V[2].gate'.

            
                Redirecting output \Y: $techmap$procmux$1160_CMP0.$xor$<stdcells.v>:808$2078.Y [2] = $techmap$procmux$1019_CMP0.$xor$<stdcells.v>:808$2078.Y [2]

            
                Removing $_XOR_ cell `$techmap$procmux$1160_CMP0.$xor$<stdcells.v>:808$2078.V[2].gate' from module `\usb_rx_phy'.

            
              Cell `$techmap$procmux$283.$and$<stdcells.v>:1203$2088.V[1].gate' is identical to cell `$techmap$procmux$283.$and$<stdcells.v>:1203$2088.V[0].gate'.

            
                Redirecting output \Y: $techmap$procmux$283.$and$<stdcells.v>:1203$2088.Y [1] = $techmap$procmux$283.$and$<stdcells.v>:1203$2088.Y [0]

            
                Removing $_AND_ cell `$techmap$procmux$283.$and$<stdcells.v>:1203$2088.V[1].gate' from module `\usb_rx_phy'.

            
              Cell `$techmap$procmux$605.$and$<stdcells.v>:1203$2106.V[1].gate' is identical to cell `$techmap$procmux$605.$and$<stdcells.v>:1203$2106.V[0].gate'.

            
                Redirecting output \Y: $techmap$procmux$605.$and$<stdcells.v>:1203$2106.Y [1] = $techmap$procmux$605.$and$<stdcells.v>:1203$2106.Y [0]

            
                Removing $_AND_ cell `$techmap$procmux$605.$and$<stdcells.v>:1203$2106.V[1].gate' from module `\usb_rx_phy'.

            
              Cell `$techmap$procmux$605.$and$<stdcells.v>:1203$2106.V[2].gate' is identical to cell `$techmap$procmux$605.$and$<stdcells.v>:1203$2106.V[0].gate'.

            
                Redirecting output \Y: $techmap$procmux$605.$and$<stdcells.v>:1203$2106.Y [2] = $techmap$procmux$605.$and$<stdcells.v>:1203$2106.Y [0]

            
                Removing $_AND_ cell `$techmap$procmux$605.$and$<stdcells.v>:1203$2106.V[2].gate' from module `\usb_rx_phy'.

            
              Cell `$techmap$procmux$605.$and$<stdcells.v>:1203$2107.V[2].gate' is identical to cell `$techmap$procmux$605.$and$<stdcells.v>:1203$2107.V[1].gate'.

            
                Redirecting output \Y: $techmap$procmux$605.$and$<stdcells.v>:1203$2107.Y [2] = $techmap$procmux$605.$and$<stdcells.v>:1203$2107.Y [1]

            
                Removing $_AND_ cell `$techmap$procmux$605.$and$<stdcells.v>:1203$2107.V[2].gate' from module `\usb_rx_phy'.

            
              Cell `$techmap$procmux$605.$and$<stdcells.v>:1203$2108.V[2].gate' is identical to cell `$techmap$procmux$605.$and$<stdcells.v>:1203$2108.V[0].gate'.

            
                Redirecting output \Y: $techmap$procmux$605.$and$<stdcells.v>:1203$2108.Y [2] = $techmap$procmux$605.$and$<stdcells.v>:1203$2108.Y [0]

            
                Removing $_AND_ cell `$techmap$procmux$605.$and$<stdcells.v>:1203$2108.V[2].gate' from module `\usb_rx_phy'.

            
              Cell `$techmap$procmux$605.$and$<stdcells.v>:1203$2110.V[1].gate' is identical to cell `$techmap$procmux$605.$and$<stdcells.v>:1203$2110.V[0].gate'.

            
                Redirecting output \Y: $techmap$procmux$605.$and$<stdcells.v>:1203$2110.Y [1] = $techmap$procmux$605.$and$<stdcells.v>:1203$2110.Y [0]

            
                Removing $_AND_ cell `$techmap$procmux$605.$and$<stdcells.v>:1203$2110.V[1].gate' from module `\usb_rx_phy'.

            
              Cell `$techmap$procmux$605.$reduce_or$<stdcells.v>:1210$2115.V[1].gate' is identical to cell `$techmap$procmux$605.$reduce_or$<stdcells.v>:1210$2114.V[1].gate'.

            
                Redirecting output \Y: $techmap$procmux$605.$reduce_or$<stdcells.v>:1210$2115.buffer [1] = $techmap$procmux$605.$reduce_or$<stdcells.v>:1210$2114.buffer [1]

            
                Removing $_OR_ cell `$techmap$procmux$605.$reduce_or$<stdcells.v>:1210$2115.V[1].gate' from module `\usb_rx_phy'.

            
              Cell `$techmap$procmux$1035_CMP0.$reduce_or$<stdcells.v>:808$2079.V[1].gate' is identical to cell `$techmap$procmux$1019_CMP0.$reduce_or$<stdcells.v>:808$2079.V[1].gate'.

            
                Redirecting output \Y: $techmap$procmux$1035_CMP0.$reduce_or$<stdcells.v>:808$2079.buffer [1] = $techmap$procmux$1019_CMP0.$reduce_or$<stdcells.v>:808$2079.buffer [1]

            
                Removing $_OR_ cell `$techmap$procmux$1035_CMP0.$reduce_or$<stdcells.v>:808$2079.V[1].gate' from module `\usb_rx_phy'.

            
              Cell `$techmap$procmux$1160_CMP0.$reduce_or$<stdcells.v>:808$2079.V[1].gate' is identical to cell `$techmap$procmux$1031_CMP0.$reduce_or$<stdcells.v>:808$2079.V[1].gate'.

            
                Redirecting output \Y: $techmap$procmux$1160_CMP0.$reduce_or$<stdcells.v>:808$2079.buffer [1] = $techmap$procmux$1031_CMP0.$reduce_or$<stdcells.v>:808$2079.buffer [1]

            
                Removing $_OR_ cell `$techmap$procmux$1160_CMP0.$reduce_or$<stdcells.v>:808$2079.V[1].gate' from module `\usb_rx_phy'.

            
            Finding identical cells in module `\usb_tx_phy'.

            
              Cell `$techmap$eq$rtl/usb_tx_phy.v:229$153.$xor$<stdcells.v>:808$2078.V[0].gate' is identical to cell `$add$rtl/usb_tx_phy.v:210$148.alu.V[0].adder.gate2'.

            
                Redirecting output \Y: $techmap$eq$rtl/usb_tx_phy.v:229$153.$xor$<stdcells.v>:808$2078.Y [0] = $add$rtl/usb_tx_phy.v:210$148.alu.V[0].adder.t2

            
                Removing $_XOR_ cell `$techmap$eq$rtl/usb_tx_phy.v:229$153.$xor$<stdcells.v>:808$2078.V[0].gate' from module `\usb_tx_phy'.

            
              Cell `$techmap$procmux$1364_CMP0.$xor$<stdcells.v>:808$2078.V[1].gate' is identical to cell `$techmap$eq$rtl/usb_tx_phy.v:229$153.$xor$<stdcells.v>:808$2078.V[1].gate'.

            
                Redirecting output \Y: $techmap$procmux$1364_CMP0.$xor$<stdcells.v>:808$2078.Y [1] = $techmap$eq$rtl/usb_tx_phy.v:229$153.$xor$<stdcells.v>:808$2078.Y [1]

            
                Removing $_XOR_ cell `$techmap$procmux$1364_CMP0.$xor$<stdcells.v>:808$2078.V[1].gate' from module `\usb_tx_phy'.

            
              Cell `$techmap$procmux$1364_CMP0.$xor$<stdcells.v>:808$2078.V[2].gate' is identical to cell `$techmap$eq$rtl/usb_tx_phy.v:229$153.$xor$<stdcells.v>:808$2078.V[2].gate'.

            
                Redirecting output \Y: $techmap$procmux$1364_CMP0.$xor$<stdcells.v>:808$2078.Y [2] = $techmap$eq$rtl/usb_tx_phy.v:229$153.$xor$<stdcells.v>:808$2078.Y [2]

            
                Removing $_XOR_ cell `$techmap$procmux$1364_CMP0.$xor$<stdcells.v>:808$2078.V[2].gate' from module `\usb_tx_phy'.

            
              Cell `$techmap$procmux$1366_CMP0.$xor$<stdcells.v>:808$2078.V[0].gate' is identical to cell `$add$rtl/usb_tx_phy.v:210$148.alu.V[0].adder.gate2'.

            
                Redirecting output \Y: $techmap$procmux$1366_CMP0.$xor$<stdcells.v>:808$2078.Y [0] = $add$rtl/usb_tx_phy.v:210$148.alu.V[0].adder.t2

            
                Removing $_XOR_ cell `$techmap$procmux$1366_CMP0.$xor$<stdcells.v>:808$2078.V[0].gate' from module `\usb_tx_phy'.

            
              Cell `$techmap$procmux$1366_CMP0.$xor$<stdcells.v>:808$2078.V[2].gate' is identical to cell `$techmap$eq$rtl/usb_tx_phy.v:229$153.$xor$<stdcells.v>:808$2078.V[2].gate'.

            
                Redirecting output \Y: $techmap$procmux$1366_CMP0.$xor$<stdcells.v>:808$2078.Y [2] = $techmap$eq$rtl/usb_tx_phy.v:229$153.$xor$<stdcells.v>:808$2078.Y [2]

            
                Removing $_XOR_ cell `$techmap$procmux$1366_CMP0.$xor$<stdcells.v>:808$2078.V[2].gate' from module `\usb_tx_phy'.

            
              Cell `$techmap$procmux$1368_CMP0.$xor$<stdcells.v>:808$2078.V[2].gate' is identical to cell `$techmap$eq$rtl/usb_tx_phy.v:229$153.$xor$<stdcells.v>:808$2078.V[2].gate'.

            
                Redirecting output \Y: $techmap$procmux$1368_CMP0.$xor$<stdcells.v>:808$2078.Y [2] = $techmap$eq$rtl/usb_tx_phy.v:229$153.$xor$<stdcells.v>:808$2078.Y [2]

            
                Removing $_XOR_ cell `$techmap$procmux$1368_CMP0.$xor$<stdcells.v>:808$2078.V[2].gate' from module `\usb_tx_phy'.

            
              Cell `$techmap$procmux$1370_CMP0.$xor$<stdcells.v>:808$2078.V[0].gate' is identical to cell `$add$rtl/usb_tx_phy.v:210$148.alu.V[0].adder.gate2'.

            
                Redirecting output \Y: $techmap$procmux$1370_CMP0.$xor$<stdcells.v>:808$2078.Y [0] = $add$rtl/usb_tx_phy.v:210$148.alu.V[0].adder.t2

            
                Removing $_XOR_ cell `$techmap$procmux$1370_CMP0.$xor$<stdcells.v>:808$2078.V[0].gate' from module `\usb_tx_phy'.

            
              Cell `$techmap$procmux$1370_CMP0.$xor$<stdcells.v>:808$2078.V[1].gate' is identical to cell `$techmap$eq$rtl/usb_tx_phy.v:229$153.$xor$<stdcells.v>:808$2078.V[1].gate'.

            
                Redirecting output \Y: $techmap$procmux$1370_CMP0.$xor$<stdcells.v>:808$2078.Y [1] = $techmap$eq$rtl/usb_tx_phy.v:229$153.$xor$<stdcells.v>:808$2078.Y [1]

            
                Removing $_XOR_ cell `$techmap$procmux$1370_CMP0.$xor$<stdcells.v>:808$2078.V[1].gate' from module `\usb_tx_phy'.

            
              Cell `$techmap$procmux$1372_CMP0.$xor$<stdcells.v>:808$2078.V[1].gate' is identical to cell `$techmap$eq$rtl/usb_tx_phy.v:229$153.$xor$<stdcells.v>:808$2078.V[1].gate'.

            
                Redirecting output \Y: $techmap$procmux$1372_CMP0.$xor$<stdcells.v>:808$2078.Y [1] = $techmap$eq$rtl/usb_tx_phy.v:229$153.$xor$<stdcells.v>:808$2078.Y [1]

            
                Removing $_XOR_ cell `$techmap$procmux$1372_CMP0.$xor$<stdcells.v>:808$2078.V[1].gate' from module `\usb_tx_phy'.

            
              Cell `$techmap$procmux$1374_CMP0.$xor$<stdcells.v>:808$2078.V[0].gate' is identical to cell `$add$rtl/usb_tx_phy.v:210$148.alu.V[0].adder.gate2'.

            
                Redirecting output \Y: $techmap$procmux$1374_CMP0.$xor$<stdcells.v>:808$2078.Y [0] = $add$rtl/usb_tx_phy.v:210$148.alu.V[0].adder.t2

            
                Removing $_XOR_ cell `$techmap$procmux$1374_CMP0.$xor$<stdcells.v>:808$2078.V[0].gate' from module `\usb_tx_phy'.

            
              Cell `$techmap$procmux$1376_CMP0.$reduce_or$<stdcells.v>:808$2079.V[1].gate' is identical to cell `$techmap$procmux$1368_CMP0.$reduce_or$<stdcells.v>:808$2079.V[1].gate'.

            
                Redirecting output \Y: $techmap$procmux$1376_CMP0.$reduce_or$<stdcells.v>:808$2079.buffer [1] = $techmap$procmux$1368_CMP0.$reduce_or$<stdcells.v>:808$2079.buffer [1]

            
                Removing $_OR_ cell `$techmap$procmux$1376_CMP0.$reduce_or$<stdcells.v>:808$2079.V[1].gate' from module `\usb_tx_phy'.

            
              Cell `$techmap$procmux$1675_CMP0.$reduce_or$<stdcells.v>:808$2079.V[1].gate' is identical to cell `$techmap$procmux$1601_CMP0.$reduce_or$<stdcells.v>:808$2079.V[1].gate'.

            
                Redirecting output \Y: $techmap$procmux$1675_CMP0.$reduce_or$<stdcells.v>:808$2079.buffer [1] = $techmap$procmux$1601_CMP0.$reduce_or$<stdcells.v>:808$2079.buffer [1]

            
                Removing $_OR_ cell `$techmap$procmux$1675_CMP0.$reduce_or$<stdcells.v>:808$2079.V[1].gate' from module `\usb_tx_phy'.

            
              Cell `$techmap$procmux$1679_CMP0.$xor$<stdcells.v>:808$2078.V[0].gate' is identical to cell `$techmap$procmux$1597_CMP0.$xor$<stdcells.v>:808$2078.V[0].gate'.

            
                Redirecting output \Y: $techmap$procmux$1679_CMP0.$xor$<stdcells.v>:808$2078.Y [0] = $techmap$procmux$1597_CMP0.$xor$<stdcells.v>:808$2078.Y [0]

            
                Removing $_XOR_ cell `$techmap$procmux$1679_CMP0.$xor$<stdcells.v>:808$2078.V[0].gate' from module `\usb_tx_phy'.

            
              Cell `$techmap$procmux$1679_CMP0.$xor$<stdcells.v>:808$2078.V[1].gate' is identical to cell `$techmap$procmux$1593_CMP0.$xor$<stdcells.v>:808$2078.V[1].gate'.

            
                Redirecting output \Y: $techmap$procmux$1679_CMP0.$xor$<stdcells.v>:808$2078.Y [1] = $techmap$procmux$1593_CMP0.$xor$<stdcells.v>:808$2078.Y [1]

            
                Removing $_XOR_ cell `$techmap$procmux$1679_CMP0.$xor$<stdcells.v>:808$2078.V[1].gate' from module `\usb_tx_phy'.

            
              Cell `$techmap$procmux$1370_CMP0.$reduce_or$<stdcells.v>:808$2079.V[1].gate' is identical to cell `$techmap$eq$rtl/usb_tx_phy.v:229$153.$reduce_or$<stdcells.v>:808$2079.V[1].gate'.

            
                Redirecting output \Y: $techmap$procmux$1370_CMP0.$reduce_or$<stdcells.v>:808$2079.buffer [1] = $techmap$eq$rtl/usb_tx_phy.v:229$153.$reduce_or$<stdcells.v>:808$2079.buffer [1]

            
                Removing $_OR_ cell `$techmap$procmux$1370_CMP0.$reduce_or$<stdcells.v>:808$2079.V[1].gate' from module `\usb_tx_phy'.

            
              Cell `$techmap$procmux$1372_CMP0.$reduce_or$<stdcells.v>:808$2079.V[1].gate' is identical to cell `$techmap$procmux$1364_CMP0.$reduce_or$<stdcells.v>:808$2079.V[1].gate'.

            
                Redirecting output \Y: $techmap$procmux$1372_CMP0.$reduce_or$<stdcells.v>:808$2079.buffer [1] = $techmap$procmux$1364_CMP0.$reduce_or$<stdcells.v>:808$2079.buffer [1]

            
                Removing $_OR_ cell `$techmap$procmux$1372_CMP0.$reduce_or$<stdcells.v>:808$2079.V[1].gate' from module `\usb_tx_phy'.

            
              Cell `$techmap$procmux$1374_CMP0.$reduce_or$<stdcells.v>:808$2079.V[1].gate' is identical to cell `$techmap$procmux$1366_CMP0.$reduce_or$<stdcells.v>:808$2079.V[1].gate'.

            
                Redirecting output \Y: $techmap$procmux$1374_CMP0.$reduce_or$<stdcells.v>:808$2079.buffer [1] = $techmap$procmux$1366_CMP0.$reduce_or$<stdcells.v>:808$2079.buffer [1]

            
                Removing $_OR_ cell `$techmap$procmux$1374_CMP0.$reduce_or$<stdcells.v>:808$2079.V[1].gate' from module `\usb_tx_phy'.

            
            Removed a total of 47 cells.


            11.4. Executing OPT_MUXTREE pass (detect dead branches in mux trees).

            
            Running muxtree optimizier on module \usb_phy..

            
              Creating internal representation of mux trees.

            
              No muxes found in this module.

            
            Running muxtree optimizier on module \usb_rx_phy..

            
              Creating internal representation of mux trees.

            
              No muxes found in this module.

            
            Running muxtree optimizier on module \usb_tx_phy..

            
              Creating internal representation of mux trees.

            
              No muxes found in this module.

            
            Removed 0 multiplexer ports.


            11.5. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).

            
              Optimizing cells in module \usb_phy.

            
              Optimizing cells in module \usb_rx_phy.

            
              Optimizing cells in module \usb_tx_phy.

            
            Performed a total of 0 changes.


            11.6. Executing OPT_SHARE pass (detect identical cells).

            
            Finding identical cells in module `\usb_phy'.

            
            Finding identical cells in module `\usb_rx_phy'.

            
            Finding identical cells in module `\usb_tx_phy'.

            
            Removed a total of 0 cells.


            11.7. Executing OPT_RMDFF pass (remove dff with constant values).

            
            Replaced 0 DFF cells.


            11.8. Executing OPT_RMUNUSED pass (remove unused cells and wires).

            
            Finding unused cells or wires in module \usb_phy..

            
              removing unused `$_AND_' cell `$add$rtl/usb_phy.v:178$6.alu.V[4].adder.gate3'.

            
              removed 146 unused temporary wires.

            
            Finding unused cells or wires in module \usb_rx_phy..

            
              removing unused `$_AND_' cell `$add$rtl/usb_rx_phy.v:399$90.alu.V[2].adder.gate3'.

            
              removing unused `$_AND_' cell `$add$rtl/usb_rx_phy.v:432$109.alu.V[2].adder.gate3'.

            
              removed 1423 unused temporary wires.

            
            Finding unused cells or wires in module \usb_tx_phy..

            
              removing unused `$_AND_' cell `$add$rtl/usb_tx_phy.v:210$148.alu.V[2].adder.gate3'.

            
              removing unused `$_AND_' cell `$add$rtl/usb_tx_phy.v:261$165.alu.V[2].adder.gate3'.

            
              removed 1209 unused temporary wires.


            11.9. Executing OPT_CONST pass (perform const folding).


            11.10. Rerunning OPT passes. (Maybe there is more to do..)


            11.11. Executing OPT_MUXTREE pass (detect dead branches in mux trees).

            
            Running muxtree optimizier on module \usb_phy..

            
              Creating internal representation of mux trees.

            
              No muxes found in this module.

            
            Running muxtree optimizier on module \usb_rx_phy..

            
              Creating internal representation of mux trees.

            
              No muxes found in this module.

            
            Running muxtree optimizier on module \usb_tx_phy..

            
              Creating internal representation of mux trees.

            
              No muxes found in this module.

            
            Removed 0 multiplexer ports.


            11.12. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).

            
              Optimizing cells in module \usb_phy.

            
              Optimizing cells in module \usb_rx_phy.

            
              Optimizing cells in module \usb_tx_phy.

            
            Performed a total of 0 changes.


            11.13. Executing OPT_SHARE pass (detect identical cells).

            
            Finding identical cells in module `\usb_phy'.

            
            Finding identical cells in module `\usb_rx_phy'.

            
            Finding identical cells in module `\usb_tx_phy'.

            
            Removed a total of 0 cells.


            11.14. Executing OPT_RMDFF pass (remove dff with constant values).

            
            Replaced 0 DFF cells.


            11.15. Executing OPT_RMUNUSED pass (remove unused cells and wires).

            
            Finding unused cells or wires in module \usb_phy..

            
            Finding unused cells or wires in module \usb_rx_phy..

            
            Finding unused cells or wires in module \usb_tx_phy..


            11.16. Executing OPT_CONST pass (perform const folding).


            11.17. Optimizing in-memory representation of design.


            11.18. Finished OPT passes. (There is nothing left to do.)


            12. Executing ABC pass (technology mapping using ABC).


            12.1. Extracting gate logic of module `\usb_phy' to `/tmp/yosys-abc-gkoDzA/input.v'..

            
            Extracted 36 gates and 48 wires to a logic network with 10 inputs and 6 outputs.


            12.1.1. Executing ABC.

            
            ABC: ABC command line: "read_verilog /tmp/yosys-abc-gkoDzA/input.v; read_library /tmp/yosys-abc-gkoDzA/stdcells.genlib; map; write_verilog /tmp/yosys-abc-gkoDzA/output.v".

            
            ABC: There is no hierarchy information.

            
            ABC: The number of gates read = 8.

            
            ABC: Read 8 gates from file "/tmp/yosys-abc-gkoDzA/stdcells.genlib".

            
            ABC: Selected 8 functionally unique gates. Time =     0.00 sec

            
            ABC: Created 4 rules and 4 matches. Time =     0.00 sec

            
            ABC: Warning: The network was strashed and balanced before mapping.

            
            ABC: A simple supergate library is derived from gate library "/tmp/yosys-abc-gkoDzA/stdcells.genlib".

            
            ABC: Loaded 9 unique 5-input supergates from "/tmp/yosys-abc-gkoDzA/stdcells.super".  Time =     0.00 sec


            12.1.2. Re-integrating ABC results.

            
            ABC RESULTS:               AND cells:       11

            
            ABC RESULTS:               INV cells:        4

            
            ABC RESULTS:               MUX cells:        4

            
            ABC RESULTS:                OR cells:        1

            
            ABC RESULTS:               XOR cells:        5

            
            ABC RESULTS:        internal signals:       32

            
            ABC RESULTS:           input signals:       10

            
            ABC RESULTS:          output signals:        6


            12.1.3. Removing temp directory `/tmp/yosys-abc-gkoDzA':

            
            Removing `/tmp/yosys-abc-gkoDzA/input.v'.

            
            Removing `/tmp/yosys-abc-gkoDzA/output.v'.

            
            Removing `/tmp/yosys-abc-gkoDzA/stdcells.genlib'.

            
            Removing `/tmp/yosys-abc-gkoDzA/stdcells.genlib_temp'.

            
            Removing `/tmp/yosys-abc-gkoDzA/stdcells.super'.

            
            Removing `/tmp/yosys-abc-gkoDzA'.


            12.2. Extracting gate logic of module `\usb_rx_phy' to `/tmp/yosys-abc-eRypnV/input.v'..

            
            Extracted 226 gates and 274 wires to a logic network with 46 inputs and 38 outputs.


            12.2.1. Executing ABC.

            
            ABC: ABC command line: "read_verilog /tmp/yosys-abc-eRypnV/input.v; read_library /tmp/yosys-abc-eRypnV/stdcells.genlib; map; write_verilog /tmp/yosys-abc-eRypnV/output.v".

            
            ABC: There is no hierarchy information.

            
            ABC: The number of gates read = 8.

            
            ABC: Read 8 gates from file "/tmp/yosys-abc-eRypnV/stdcells.genlib".

            
            ABC: Selected 8 functionally unique gates. Time =     0.00 sec

            
            ABC: Created 4 rules and 4 matches. Time =     0.00 sec

            
            ABC: Warning: The network was strashed and balanced before mapping.

            
            ABC: A simple supergate library is derived from gate library "/tmp/yosys-abc-eRypnV/stdcells.genlib".

            
            ABC: Loaded 9 unique 5-input supergates from "/tmp/yosys-abc-eRypnV/stdcells.super".  Time =     0.00 sec


            12.2.2. Re-integrating ABC results.

            
            ABC RESULTS:               AND cells:      101

            
            ABC RESULTS:               INV cells:       25

            
            ABC RESULTS:               MUX cells:       16

            
            ABC RESULTS:                OR cells:       51

            
            ABC RESULTS:               XOR cells:        6

            
            ABC RESULTS:        internal signals:      190

            
            ABC RESULTS:           input signals:       46

            
            ABC RESULTS:          output signals:       38


            12.2.3. Removing temp directory `/tmp/yosys-abc-eRypnV':

            
            Removing `/tmp/yosys-abc-eRypnV/input.v'.

            
            Removing `/tmp/yosys-abc-eRypnV/output.v'.

            
            Removing `/tmp/yosys-abc-eRypnV/stdcells.genlib'.

            
            Removing `/tmp/yosys-abc-eRypnV/stdcells.genlib_temp'.

            
            Removing `/tmp/yosys-abc-eRypnV/stdcells.super'.

            
            Removing `/tmp/yosys-abc-eRypnV'.


            12.3. Extracting gate logic of module `\usb_tx_phy' to `/tmp/yosys-abc-HZdAHg/input.v'..

            
            Extracted 244 gates and 302 wires to a logic network with 56 inputs and 36 outputs.


            12.3.1. Executing ABC.

            
            ABC: ABC command line: "read_verilog /tmp/yosys-abc-HZdAHg/input.v; read_library /tmp/yosys-abc-HZdAHg/stdcells.genlib; map; write_verilog /tmp/yosys-abc-HZdAHg/output.v".

            
            ABC: There is no hierarchy information.

            
            ABC: The number of gates read = 8.

            
            ABC: Read 8 gates from file "/tmp/yosys-abc-HZdAHg/stdcells.genlib".

            
            ABC: Selected 8 functionally unique gates. Time =     0.00 sec

            
            ABC: Created 4 rules and 4 matches. Time =     0.00 sec

            
            ABC: Warning: The network was strashed and balanced before mapping.

            
            ABC: A simple supergate library is derived from gate library "/tmp/yosys-abc-HZdAHg/stdcells.genlib".

            
            ABC: Loaded 9 unique 5-input supergates from "/tmp/yosys-abc-HZdAHg/stdcells.super".  Time =     0.00 sec


            12.3.2. Re-integrating ABC results.

            
            ABC RESULTS:               AND cells:      102

            
            ABC RESULTS:               INV cells:       24

            
            ABC RESULTS:               MUX cells:       26

            
            ABC RESULTS:                OR cells:       42

            
            ABC RESULTS:               XOR cells:        6

            
            ABC RESULTS:        internal signals:      210

            
            ABC RESULTS:           input signals:       56

            
            ABC RESULTS:          output signals:       36


            12.3.3. Removing temp directory `/tmp/yosys-abc-HZdAHg':

            
            Removing `/tmp/yosys-abc-HZdAHg/input.v'.

            
            Removing `/tmp/yosys-abc-HZdAHg/output.v'.

            
            Removing `/tmp/yosys-abc-HZdAHg/stdcells.genlib'.

            
            Removing `/tmp/yosys-abc-HZdAHg/stdcells.genlib_temp'.

            
            Removing `/tmp/yosys-abc-HZdAHg/stdcells.super'.

            
            Removing `/tmp/yosys-abc-HZdAHg'.


            13. Executing OPT pass (performing simple optimizations).


            13.1. Optimizing in-memory representation of design.


            13.2. Executing OPT_CONST pass (perform const folding).


            13.3. Executing OPT_SHARE pass (detect identical cells).

            
            Full command line: opt_share -nomux

            
            Finding identical cells in module `\usb_phy'.

            
            Finding identical cells in module `\usb_rx_phy'.

            
            Finding identical cells in module `\usb_tx_phy'.

            
            Removed a total of 0 cells.


            13.4. Executing OPT_MUXTREE pass (detect dead branches in mux trees).

            
            Running muxtree optimizier on module \usb_phy..

            
              Creating internal representation of mux trees.

            
              No muxes found in this module.

            
            Running muxtree optimizier on module \usb_rx_phy..

            
              Creating internal representation of mux trees.

            
              No muxes found in this module.

            
            Running muxtree optimizier on module \usb_tx_phy..

            
              Creating internal representation of mux trees.

            
              No muxes found in this module.

            
            Removed 0 multiplexer ports.


            13.5. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).

            
              Optimizing cells in module \usb_phy.

            
              Optimizing cells in module \usb_rx_phy.

            
              Optimizing cells in module \usb_tx_phy.

            
            Performed a total of 0 changes.


            13.6. Executing OPT_SHARE pass (detect identical cells).

            
            Finding identical cells in module `\usb_phy'.

            
            Finding identical cells in module `\usb_rx_phy'.

            
            Finding identical cells in module `\usb_tx_phy'.

            
            Removed a total of 0 cells.


            13.7. Executing OPT_RMDFF pass (remove dff with constant values).

            
            Replaced 0 DFF cells.


            13.8. Executing OPT_RMUNUSED pass (remove unused cells and wires).

            
            Finding unused cells or wires in module \usb_phy..

            
              removed 29 unused temporary wires.

            
            Finding unused cells or wires in module \usb_rx_phy..

            
              removing unused non-port wire \change.

            
              removing unused non-port wire \dpll_next_state.

            
              removing unused non-port wire \drop_bit.

            
              removing unused non-port wire \fs_next_state.

            
              removing unused non-port wire \j.

            
              removing unused non-port wire \k.

            
              removing unused non-port wire \sync_err_d.

            
              removing unused non-port wire \synced_d.

            
              removed 217 unused temporary wires.

            
            Finding unused cells or wires in module \usb_tx_phy..

            
              removing unused non-port wire \hold.

            
              removing unused non-port wire \ld_eop_d.

            
              removing unused non-port wire \ld_sop_d.

            
              removing unused non-port wire \next_state.

            
              removing unused non-port wire \sft_done_e.

            
              removing unused non-port wire \stuff.

            
              removed 217 unused temporary wires.


            13.9. Executing OPT_CONST pass (perform const folding).


            13.10. Optimizing in-memory representation of design.


            13.11. Finished OPT passes. (There is nothing left to do.)


            14. Executing Verilog backend.

            
            Full command line: write_verilog -noattr output/synth.v

            
            Dumping module `\usb_phy'.

            
              renaming `$0\rst_cnt[4:0]' to `_00_'.

            
              renaming `$0\usb_rst[0:0]' to `_01_'.

            
              renaming `$abc$2136$g00' to `_21_'.

            
              renaming `$abc$2136$g01' to `_22_'.

            
              renaming `$abc$2136$g02' to `_23_'.

            
              renaming `$abc$2136$g03' to `_24_'.

            
              renaming `$abc$2136$g04' to `_25_'.

            
              renaming `$abc$2136$g05' to `_26_'.

            
              renaming `$abc$2136$g06' to `_27_'.

            
              renaming `$abc$2136$g07' to `_28_'.

            
              renaming `$abc$2136$g08' to `_29_'.

            
              renaming `$abc$2136$g09' to `_30_'.

            
              renaming `$abc$2136$g10' to `_31_'.

            
              renaming `$abc$2136$g11' to `_32_'.

            
              renaming `$abc$2136$g12' to `_33_'.

            
              renaming `$abc$2136$g13' to `_34_'.

            
              renaming `$abc$2136$g14' to `_35_'.

            
              renaming `$abc$2136$g15' to `_36_'.

            
              renaming `$abc$2136$g16' to `_37_'.

            
              renaming `$abc$2136$g17' to `_38_'.

            
              renaming `$abc$2136$g18' to `_39_'.

            
              renaming `$abc$2136$g19' to `_40_'.

            
              renaming `$abc$2136$g20' to `_41_'.

            
              renaming `$abc$2136$g21' to `_42_'.

            
              renaming `$abc$2136$g22' to `_43_'.

            
              renaming `$abc$2136$g23' to `_44_'.

            
              renaming `$abc$2136$g24' to `_45_'.

            
              renaming `$abc$2136$n16' to `_02_'.

            
              renaming `$abc$2136$n17_1' to `_03_'.

            
              renaming `$abc$2136$n18' to `_04_'.

            
              renaming `$abc$2136$n19_1' to `_05_'.

            
              renaming `$abc$2136$n20' to `_06_'.

            
              renaming `$abc$2136$n21' to `_07_'.

            
              renaming `$abc$2136$n22' to `_08_'.

            
              renaming `$abc$2136$n23' to `_09_'.

            
              renaming `$abc$2136$n25' to `_10_'.

            
              renaming `$abc$2136$n26' to `_11_'.

            
              renaming `$abc$2136$n28' to `_12_'.

            
              renaming `$abc$2136$n29' to `_13_'.

            
              renaming `$abc$2136$n30' to `_14_'.

            
              renaming `$abc$2136$n32_1' to `_15_'.

            
              renaming `$abc$2136$n33_1' to `_16_'.

            
              renaming `$abc$2136$n34_1' to `_17_'.

            
              renaming `$abc$2136$n36_1' to `_18_'.

            
              renaming `$abc$2136$n37' to `_19_'.

            
              renaming `$abc$2136$n38_1' to `_20_'.

            
              renaming `$procdff$1980.V[0].ff' to `_46_'.

            
              renaming `$procdff$1980.V[1].ff' to `_47_'.

            
              renaming `$procdff$1980.V[2].ff' to `_48_'.

            
              renaming `$procdff$1980.V[3].ff' to `_49_'.

            
              renaming `$procdff$1980.V[4].ff' to `_50_'.

            
              renaming `$procdff$1981.V[0].ff' to `_51_'.

            
            Dumping module `\usb_rx_phy'.

            
              renaming `$0\bit_cnt[2:0]' to `_000_'.

            
              renaming `$0\bit_stuff_err[0:0]' to `_001_'.

            
              renaming `$0\byte_err[0:0]' to `_002_'.

            
              renaming `$0\dpll_state[1:0]' to `_003_'.

            
              renaming `$0\fs_state[2:0]' to `_004_'.

            
              renaming `$0\hold_reg[7:0]' to `_005_'.

            
              renaming `$0\one_cnt[2:0]' to `_006_'.

            
              renaming `$0\rx_active[0:0]' to `_007_'.

            
              renaming `$0\rx_valid1[0:0]' to `_008_'.

            
              renaming `$0\rx_valid[0:0]' to `_009_'.

            
              renaming `$0\rx_valid_r[0:0]' to `_010_'.

            
              renaming `$0\rxd_s[0:0]' to `_011_'.

            
              renaming `$0\rxdn_s[0:0]' to `_012_'.

            
              renaming `$0\rxdn_s_r[0:0]' to `_013_'.

            
              renaming `$0\rxdp_s[0:0]' to `_014_'.

            
              renaming `$0\rxdp_s_r[0:0]' to `_015_'.

            
              renaming `$0\sd_nrzi[0:0]' to `_016_'.

            
              renaming `$0\sd_r[0:0]' to `_017_'.

            
              renaming `$0\se0_s[0:0]' to `_018_'.

            
              renaming `$0\shift_en[0:0]' to `_019_'.

            
              renaming `$0\sync_err[0:0]' to `_020_'.

            
              renaming `$abc$2137$g000' to `_182_'.

            
              renaming `$abc$2137$g001' to `_183_'.

            
              renaming `$abc$2137$g002' to `_184_'.

            
              renaming `$abc$2137$g003' to `_185_'.

            
              renaming `$abc$2137$g004' to `_186_'.

            
              renaming `$abc$2137$g005' to `_187_'.

            
              renaming `$abc$2137$g006' to `_188_'.

            
              renaming `$abc$2137$g007' to `_189_'.

            
              renaming `$abc$2137$g008' to `_190_'.

            
              renaming `$abc$2137$g009' to `_191_'.

            
              renaming `$abc$2137$g010' to `_192_'.

            
              renaming `$abc$2137$g011' to `_193_'.

            
              renaming `$abc$2137$g012' to `_194_'.

            
              renaming `$abc$2137$g013' to `_195_'.

            
              renaming `$abc$2137$g014' to `_196_'.

            
              renaming `$abc$2137$g015' to `_197_'.

            
              renaming `$abc$2137$g016' to `_198_'.

            
              renaming `$abc$2137$g017' to `_199_'.

            
              renaming `$abc$2137$g018' to `_200_'.

            
              renaming `$abc$2137$g019' to `_201_'.

            
              renaming `$abc$2137$g020' to `_202_'.

            
              renaming `$abc$2137$g021' to `_203_'.

            
              renaming `$abc$2137$g022' to `_204_'.

            
              renaming `$abc$2137$g023' to `_205_'.

            
              renaming `$abc$2137$g024' to `_206_'.

            
              renaming `$abc$2137$g025' to `_207_'.

            
              renaming `$abc$2137$g026' to `_208_'.

            
              renaming `$abc$2137$g027' to `_209_'.

            
              renaming `$abc$2137$g028' to `_210_'.

            
              renaming `$abc$2137$g029' to `_211_'.

            
              renaming `$abc$2137$g030' to `_212_'.

            
              renaming `$abc$2137$g031' to `_213_'.

            
              renaming `$abc$2137$g032' to `_214_'.

            
              renaming `$abc$2137$g033' to `_215_'.

            
              renaming `$abc$2137$g034' to `_216_'.

            
              renaming `$abc$2137$g035' to `_217_'.

            
              renaming `$abc$2137$g036' to `_218_'.

            
              renaming `$abc$2137$g037' to `_219_'.

            
              renaming `$abc$2137$g038' to `_220_'.

            
              renaming `$abc$2137$g039' to `_221_'.

            
              renaming `$abc$2137$g040' to `_222_'.

            
              renaming `$abc$2137$g041' to `_223_'.

            
              renaming `$abc$2137$g042' to `_224_'.

            
              renaming `$abc$2137$g043' to `_225_'.

            
              renaming `$abc$2137$g044' to `_226_'.

            
              renaming `$abc$2137$g045' to `_227_'.

            
              renaming `$abc$2137$g046' to `_228_'.

            
              renaming `$abc$2137$g047' to `_229_'.

            
              renaming `$abc$2137$g048' to `_230_'.

            
              renaming `$abc$2137$g049' to `_231_'.

            
              renaming `$abc$2137$g050' to `_232_'.

            
              renaming `$abc$2137$g051' to `_233_'.

            
              renaming `$abc$2137$g052' to `_234_'.

            
              renaming `$abc$2137$g053' to `_235_'.

            
              renaming `$abc$2137$g054' to `_236_'.

            
              renaming `$abc$2137$g055' to `_237_'.

            
              renaming `$abc$2137$g056' to `_238_'.

            
              renaming `$abc$2137$g057' to `_239_'.

            
              renaming `$abc$2137$g058' to `_240_'.

            
              renaming `$abc$2137$g059' to `_241_'.

            
              renaming `$abc$2137$g060' to `_242_'.

            
              renaming `$abc$2137$g061' to `_243_'.

            
              renaming `$abc$2137$g062' to `_244_'.

            
              renaming `$abc$2137$g063' to `_245_'.

            
              renaming `$abc$2137$g064' to `_246_'.

            
              renaming `$abc$2137$g065' to `_247_'.

            
              renaming `$abc$2137$g066' to `_248_'.

            
              renaming `$abc$2137$g067' to `_249_'.

            
              renaming `$abc$2137$g068' to `_250_'.

            
              renaming `$abc$2137$g069' to `_251_'.

            
              renaming `$abc$2137$g070' to `_252_'.

            
              renaming `$abc$2137$g071' to `_253_'.

            
              renaming `$abc$2137$g072' to `_254_'.

            
              renaming `$abc$2137$g073' to `_255_'.

            
              renaming `$abc$2137$g074' to `_256_'.

            
              renaming `$abc$2137$g075' to `_257_'.

            
              renaming `$abc$2137$g076' to `_258_'.

            
              renaming `$abc$2137$g077' to `_259_'.

            
              renaming `$abc$2137$g078' to `_260_'.

            
              renaming `$abc$2137$g079' to `_261_'.

            
              renaming `$abc$2137$g080' to `_262_'.

            
              renaming `$abc$2137$g081' to `_263_'.

            
              renaming `$abc$2137$g082' to `_264_'.

            
              renaming `$abc$2137$g083' to `_265_'.

            
              renaming `$abc$2137$g084' to `_266_'.

            
              renaming `$abc$2137$g085' to `_267_'.

            
              renaming `$abc$2137$g086' to `_268_'.

            
              renaming `$abc$2137$g087' to `_269_'.

            
              renaming `$abc$2137$g088' to `_270_'.

            
              renaming `$abc$2137$g089' to `_271_'.

            
              renaming `$abc$2137$g090' to `_272_'.

            
              renaming `$abc$2137$g091' to `_273_'.

            
              renaming `$abc$2137$g092' to `_274_'.

            
              renaming `$abc$2137$g093' to `_275_'.

            
              renaming `$abc$2137$g094' to `_276_'.

            
              renaming `$abc$2137$g095' to `_277_'.

            
              renaming `$abc$2137$g096' to `_278_'.

            
              renaming `$abc$2137$g097' to `_279_'.

            
              renaming `$abc$2137$g098' to `_280_'.

            
              renaming `$abc$2137$g099' to `_281_'.

            
              renaming `$abc$2137$g100' to `_282_'.

            
              renaming `$abc$2137$g101' to `_283_'.

            
              renaming `$abc$2137$g102' to `_284_'.

            
              renaming `$abc$2137$g103' to `_285_'.

            
              renaming `$abc$2137$g104' to `_286_'.

            
              renaming `$abc$2137$g105' to `_287_'.

            
              renaming `$abc$2137$g106' to `_288_'.

            
              renaming `$abc$2137$g107' to `_289_'.

            
              renaming `$abc$2137$g108' to `_290_'.

            
              renaming `$abc$2137$g109' to `_291_'.

            
              renaming `$abc$2137$g110' to `_292_'.

            
              renaming `$abc$2137$g111' to `_293_'.

            
              renaming `$abc$2137$g112' to `_294_'.

            
              renaming `$abc$2137$g113' to `_295_'.

            
              renaming `$abc$2137$g114' to `_296_'.

            
              renaming `$abc$2137$g115' to `_297_'.

            
              renaming `$abc$2137$g116' to `_298_'.

            
              renaming `$abc$2137$g117' to `_299_'.

            
              renaming `$abc$2137$g118' to `_300_'.

            
              renaming `$abc$2137$g119' to `_301_'.

            
              renaming `$abc$2137$g120' to `_302_'.

            
              renaming `$abc$2137$g121' to `_303_'.

            
              renaming `$abc$2137$g122' to `_304_'.

            
              renaming `$abc$2137$g123' to `_305_'.

            
              renaming `$abc$2137$g124' to `_306_'.

            
              renaming `$abc$2137$g125' to `_307_'.

            
              renaming `$abc$2137$g126' to `_308_'.

            
              renaming `$abc$2137$g127' to `_309_'.

            
              renaming `$abc$2137$g128' to `_310_'.

            
              renaming `$abc$2137$g129' to `_311_'.

            
              renaming `$abc$2137$g130' to `_312_'.

            
              renaming `$abc$2137$g131' to `_313_'.

            
              renaming `$abc$2137$g132' to `_314_'.

            
              renaming `$abc$2137$g133' to `_315_'.

            
              renaming `$abc$2137$g134' to `_316_'.

            
              renaming `$abc$2137$g135' to `_317_'.

            
              renaming `$abc$2137$g136' to `_318_'.

            
              renaming `$abc$2137$g137' to `_319_'.

            
              renaming `$abc$2137$g138' to `_320_'.

            
              renaming `$abc$2137$g139' to `_321_'.

            
              renaming `$abc$2137$g140' to `_322_'.

            
              renaming `$abc$2137$g141' to `_323_'.

            
              renaming `$abc$2137$g142' to `_324_'.

            
              renaming `$abc$2137$g143' to `_325_'.

            
              renaming `$abc$2137$g144' to `_326_'.

            
              renaming `$abc$2137$g145' to `_327_'.

            
              renaming `$abc$2137$g146' to `_328_'.

            
              renaming `$abc$2137$g147' to `_329_'.

            
              renaming `$abc$2137$g148' to `_330_'.

            
              renaming `$abc$2137$g149' to `_331_'.

            
              renaming `$abc$2137$g150' to `_332_'.

            
              renaming `$abc$2137$g151' to `_333_'.

            
              renaming `$abc$2137$g152' to `_334_'.

            
              renaming `$abc$2137$g153' to `_335_'.

            
              renaming `$abc$2137$g154' to `_336_'.

            
              renaming `$abc$2137$g155' to `_337_'.

            
              renaming `$abc$2137$g156' to `_338_'.

            
              renaming `$abc$2137$g157' to `_339_'.

            
              renaming `$abc$2137$g158' to `_340_'.

            
              renaming `$abc$2137$g159' to `_341_'.

            
              renaming `$abc$2137$g160' to `_342_'.

            
              renaming `$abc$2137$g161' to `_343_'.

            
              renaming `$abc$2137$g162' to `_344_'.

            
              renaming `$abc$2137$g163' to `_345_'.

            
              renaming `$abc$2137$g164' to `_346_'.

            
              renaming `$abc$2137$g165' to `_347_'.

            
              renaming `$abc$2137$g166' to `_348_'.

            
              renaming `$abc$2137$g167' to `_349_'.

            
              renaming `$abc$2137$g168' to `_350_'.

            
              renaming `$abc$2137$g169' to `_351_'.

            
              renaming `$abc$2137$g170' to `_352_'.

            
              renaming `$abc$2137$g171' to `_353_'.

            
              renaming `$abc$2137$g172' to `_354_'.

            
              renaming `$abc$2137$g173' to `_355_'.

            
              renaming `$abc$2137$g174' to `_356_'.

            
              renaming `$abc$2137$g175' to `_357_'.

            
              renaming `$abc$2137$g176' to `_358_'.

            
              renaming `$abc$2137$g177' to `_359_'.

            
              renaming `$abc$2137$g178' to `_360_'.

            
              renaming `$abc$2137$g179' to `_361_'.

            
              renaming `$abc$2137$g180' to `_362_'.

            
              renaming `$abc$2137$g181' to `_363_'.

            
              renaming `$abc$2137$g182' to `_364_'.

            
              renaming `$abc$2137$g183' to `_365_'.

            
              renaming `$abc$2137$g184' to `_366_'.

            
              renaming `$abc$2137$g185' to `_367_'.

            
              renaming `$abc$2137$g186' to `_368_'.

            
              renaming `$abc$2137$g187' to `_369_'.

            
              renaming `$abc$2137$g188' to `_370_'.

            
              renaming `$abc$2137$g189' to `_371_'.

            
              renaming `$abc$2137$g190' to `_372_'.

            
              renaming `$abc$2137$g191' to `_373_'.

            
              renaming `$abc$2137$g192' to `_374_'.

            
              renaming `$abc$2137$g193' to `_375_'.

            
              renaming `$abc$2137$g194' to `_376_'.

            
              renaming `$abc$2137$g195' to `_377_'.

            
              renaming `$abc$2137$g196' to `_378_'.

            
              renaming `$abc$2137$g197' to `_379_'.

            
              renaming `$abc$2137$g198' to `_380_'.

            
              renaming `$abc$2137$n100_1' to `_021_'.

            
              renaming `$abc$2137$n101' to `_022_'.

            
              renaming `$abc$2137$n102_1' to `_023_'.

            
              renaming `$abc$2137$n103_1' to `_024_'.

            
              renaming `$abc$2137$n104_1' to `_025_'.

            
              renaming `$abc$2137$n105_1' to `_026_'.

            
              renaming `$abc$2137$n106_1' to `_027_'.

            
              renaming `$abc$2137$n107_1' to `_028_'.

            
              renaming `$abc$2137$n108_1' to `_029_'.

            
              renaming `$abc$2137$n109' to `_030_'.

            
              renaming `$abc$2137$n110' to `_031_'.

            
              renaming `$abc$2137$n111' to `_032_'.

            
              renaming `$abc$2137$n112' to `_033_'.

            
              renaming `$abc$2137$n113' to `_034_'.

            
              renaming `$abc$2137$n114' to `_035_'.

            
              renaming `$abc$2137$n115' to `_036_'.

            
              renaming `$abc$2137$n116' to `_037_'.

            
              renaming `$abc$2137$n117_1' to `_038_'.

            
              renaming `$abc$2137$n119_1' to `_039_'.

            
              renaming `$abc$2137$n124' to `_040_'.

            
              renaming `$abc$2137$n125' to `_041_'.

            
              renaming `$abc$2137$n126_1' to `_042_'.

            
              renaming `$abc$2137$n127' to `_043_'.

            
              renaming `$abc$2137$n128' to `_044_'.

            
              renaming `$abc$2137$n129' to `_045_'.

            
              renaming `$abc$2137$n131' to `_046_'.

            
              renaming `$abc$2137$n132' to `_047_'.

            
              renaming `$abc$2137$n133' to `_048_'.

            
              renaming `$abc$2137$n135' to `_049_'.

            
              renaming `$abc$2137$n136_1' to `_050_'.

            
              renaming `$abc$2137$n137_1' to `_051_'.

            
              renaming `$abc$2137$n138_1' to `_052_'.

            
              renaming `$abc$2137$n140_1' to `_053_'.

            
              renaming `$abc$2137$n144_1' to `_054_'.

            
              renaming `$abc$2137$n145_1' to `_055_'.

            
              renaming `$abc$2137$n147_1' to `_056_'.

            
              renaming `$abc$2137$n148_1' to `_057_'.

            
              renaming `$abc$2137$n149_1' to `_058_'.

            
              renaming `$abc$2137$n150_1' to `_059_'.

            
              renaming `$abc$2137$n151_1' to `_060_'.

            
              renaming `$abc$2137$n152_1' to `_061_'.

            
              renaming `$abc$2137$n153_1' to `_062_'.

            
              renaming `$abc$2137$n154_1' to `_063_'.

            
              renaming `$abc$2137$n155_1' to `_064_'.

            
              renaming `$abc$2137$n156' to `_065_'.

            
              renaming `$abc$2137$n157' to `_066_'.

            
              renaming `$abc$2137$n158' to `_067_'.

            
              renaming `$abc$2137$n159' to `_068_'.

            
              renaming `$abc$2137$n160' to `_069_'.

            
              renaming `$abc$2137$n161' to `_070_'.

            
              renaming `$abc$2137$n163_1' to `_071_'.

            
              renaming `$abc$2137$n164_1' to `_072_'.

            
              renaming `$abc$2137$n167_1' to `_073_'.

            
              renaming `$abc$2137$n168' to `_074_'.

            
              renaming `$abc$2137$n169_1' to `_075_'.

            
              renaming `$abc$2137$n170_1' to `_076_'.

            
              renaming `$abc$2137$n171' to `_077_'.

            
              renaming `$abc$2137$n172_1' to `_078_'.

            
              renaming `$abc$2137$n173' to `_079_'.

            
              renaming `$abc$2137$n174_1' to `_080_'.

            
              renaming `$abc$2137$n175' to `_081_'.

            
              renaming `$abc$2137$n176_1' to `_082_'.

            
              renaming `$abc$2137$n177' to `_083_'.

            
              renaming `$abc$2137$n179' to `_084_'.

            
              renaming `$abc$2137$n180_1' to `_085_'.

            
              renaming `$abc$2137$n181' to `_086_'.

            
              renaming `$abc$2137$n182_1' to `_087_'.

            
              renaming `$abc$2137$n183' to `_088_'.

            
              renaming `$abc$2137$n184_1' to `_089_'.

            
              renaming `$abc$2137$n185' to `_090_'.

            
              renaming `$abc$2137$n187' to `_091_'.

            
              renaming `$abc$2137$n188_1' to `_092_'.

            
              renaming `$abc$2137$n189' to `_093_'.

            
              renaming `$abc$2137$n190_1' to `_094_'.

            
              renaming `$abc$2137$n191' to `_095_'.

            
              renaming `$abc$2137$n193' to `_096_'.

            
              renaming `$abc$2137$n194' to `_097_'.

            
              renaming `$abc$2137$n195' to `_098_'.

            
              renaming `$abc$2137$n196' to `_099_'.

            
              renaming `$abc$2137$n197' to `_100_'.

            
              renaming `$abc$2137$n198' to `_101_'.

            
              renaming `$abc$2137$n200' to `_102_'.

            
              renaming `$abc$2137$n202' to `_103_'.

            
              renaming `$abc$2137$n203' to `_104_'.

            
              renaming `$abc$2137$n212' to `_105_'.

            
              renaming `$abc$2137$n213' to `_106_'.

            
              renaming `$abc$2137$n215' to `_107_'.

            
              renaming `$abc$2137$n216' to `_108_'.

            
              renaming `$abc$2137$n218' to `_109_'.

            
              renaming `$abc$2137$n219' to `_110_'.

            
              renaming `$abc$2137$n220' to `_111_'.

            
              renaming `$abc$2137$n222' to `_112_'.

            
              renaming `$abc$2137$n223' to `_113_'.

            
              renaming `$abc$2137$n224' to `_114_'.

            
              renaming `$abc$2137$n225_1' to `_115_'.

            
              renaming `$abc$2137$n227' to `_116_'.

            
              renaming `$abc$2137$n228' to `_117_'.

            
              renaming `$abc$2137$n229' to `_118_'.

            
              renaming `$abc$2137$n230' to `_119_'.

            
              renaming `$abc$2137$n231' to `_120_'.

            
              renaming `$abc$2137$n234' to `_121_'.

            
              renaming `$abc$2137$n235' to `_122_'.

            
              renaming `$abc$2137$n236' to `_123_'.

            
              renaming `$abc$2137$n237' to `_124_'.

            
              renaming `$abc$2137$n238' to `_125_'.

            
              renaming `$abc$2137$n239' to `_126_'.

            
              renaming `$abc$2137$n240' to `_127_'.

            
              renaming `$abc$2137$n241' to `_128_'.

            
              renaming `$abc$2137$n242' to `_129_'.

            
              renaming `$abc$2137$n244' to `_130_'.

            
              renaming `$abc$2137$n245' to `_131_'.

            
              renaming `$abc$2137$n246' to `_132_'.

            
              renaming `$abc$2137$n247' to `_133_'.

            
              renaming `$abc$2137$n248' to `_134_'.

            
              renaming `$abc$2137$n250' to `_135_'.

            
              renaming `$abc$2137$n252' to `_136_'.

            
              renaming `$abc$2137$n253' to `_137_'.

            
              renaming `$abc$2137$n254' to `_138_'.

            
              renaming `$abc$2137$n255' to `_139_'.

            
              renaming `$abc$2137$n256' to `_140_'.

            
              renaming `$abc$2137$n257' to `_141_'.

            
              renaming `$abc$2137$n258' to `_142_'.

            
              renaming `$abc$2137$n259' to `_143_'.

            
              renaming `$abc$2137$n260' to `_144_'.

            
              renaming `$abc$2137$n261' to `_145_'.

            
              renaming `$abc$2137$n262' to `_146_'.

            
              renaming `$abc$2137$n263' to `_147_'.

            
              renaming `$abc$2137$n264' to `_148_'.

            
              renaming `$abc$2137$n265' to `_149_'.

            
              renaming `$abc$2137$n267' to `_150_'.

            
              renaming `$abc$2137$n268' to `_151_'.

            
              renaming `$abc$2137$n269' to `_152_'.

            
              renaming `$abc$2137$n270' to `_153_'.

            
              renaming `$abc$2137$n273' to `_154_'.

            
              renaming `$abc$2137$n274' to `_155_'.

            
              renaming `$abc$2137$n276' to `_156_'.

            
              renaming `$abc$2137$n277' to `_157_'.

            
              renaming `$abc$2137$n278' to `_158_'.

            
              renaming `$abc$2137$n279' to `_159_'.

            
              renaming `$abc$2137$n283' to `_160_'.

            
              renaming `$abc$2137$n284' to `_161_'.

            
              renaming `$abc$2137$n285' to `_162_'.

            
              renaming `$abc$2137$n287' to `_163_'.

            
              renaming `$abc$2137$n288' to `_164_'.

            
              renaming `$abc$2137$n289' to `_165_'.

            
              renaming `$abc$2137$n84' to `_166_'.

            
              renaming `$abc$2137$n85' to `_167_'.

            
              renaming `$abc$2137$n86' to `_168_'.

            
              renaming `$abc$2137$n87' to `_169_'.

            
              renaming `$abc$2137$n88' to `_170_'.

            
              renaming `$abc$2137$n89' to `_171_'.

            
              renaming `$abc$2137$n90' to `_172_'.

            
              renaming `$abc$2137$n91_1' to `_173_'.

            
              renaming `$abc$2137$n92' to `_174_'.

            
              renaming `$abc$2137$n93_1' to `_175_'.

            
              renaming `$abc$2137$n94' to `_176_'.

            
              renaming `$abc$2137$n95' to `_177_'.

            
              renaming `$abc$2137$n96' to `_178_'.

            
              renaming `$abc$2137$n97' to `_179_'.

            
              renaming `$abc$2137$n98_1' to `_180_'.

            
              renaming `$abc$2137$n99' to `_181_'.

            
              renaming `$procdff$1982.V[0].ff' to `_381_'.

            
              renaming `$procdff$1983.V[0].ff' to `_382_'.

            
              renaming `$procdff$1984.V[0].ff' to `_383_'.

            
              renaming `$procdff$1985.V[0].ff' to `_384_'.

            
              renaming `$procdff$1986.V[0].ff' to `_385_'.

            
              renaming `$procdff$1987.V[0].ff' to `_386_'.

            
              renaming `$procdff$1988.V[0].ff' to `_387_'.

            
              renaming `$procdff$1989.V[0].ff' to `_388_'.

            
              renaming `$procdff$1990.V[0].ff' to `_389_'.

            
              renaming `$procdff$1991.V[0].ff' to `_390_'.

            
              renaming `$procdff$1992.V[0].ff' to `_391_'.

            
              renaming `$procdff$1993.V[0].ff' to `_392_'.

            
              renaming `$procdff$1994.V[0].ff' to `_393_'.

            
              renaming `$procdff$1995.V[0].ff' to `_394_'.

            
              renaming `$procdff$1996.V[0].ff' to `_395_'.

            
              renaming `$procdff$1997.V[0].ff' to `_396_'.

            
              renaming `$procdff$1997.V[1].ff' to `_397_'.

            
              renaming `$procdff$1998.V[0].ff' to `_398_'.

            
              renaming `$procdff$1999.V[0].ff' to `_399_'.

            
              renaming `$procdff$2000.V[0].ff' to `_400_'.

            
              renaming `$procdff$2001.V[0].ff' to `_401_'.

            
              renaming `$procdff$2001.V[1].ff' to `_402_'.

            
              renaming `$procdff$2001.V[2].ff' to `_403_'.

            
              renaming `$procdff$2002.V[0].ff' to `_404_'.

            
              renaming `$procdff$2003.V[0].ff' to `_405_'.

            
              renaming `$procdff$2004.V[0].ff' to `_406_'.

            
              renaming `$procdff$2005.V[0].ff' to `_407_'.

            
              renaming `$procdff$2006.V[0].ff' to `_408_'.

            
              renaming `$procdff$2006.V[1].ff' to `_409_'.

            
              renaming `$procdff$2006.V[2].ff' to `_410_'.

            
              renaming `$procdff$2007.V[0].ff' to `_411_'.

            
              renaming `$procdff$2008.V[0].ff' to `_412_'.

            
              renaming `$procdff$2009.V[0].ff' to `_413_'.

            
              renaming `$procdff$2009.V[1].ff' to `_414_'.

            
              renaming `$procdff$2009.V[2].ff' to `_415_'.

            
              renaming `$procdff$2009.V[3].ff' to `_416_'.

            
              renaming `$procdff$2009.V[4].ff' to `_417_'.

            
              renaming `$procdff$2009.V[5].ff' to `_418_'.

            
              renaming `$procdff$2009.V[6].ff' to `_419_'.

            
              renaming `$procdff$2009.V[7].ff' to `_420_'.

            
              renaming `$procdff$2010.V[0].ff' to `_421_'.

            
              renaming `$procdff$2010.V[1].ff' to `_422_'.

            
              renaming `$procdff$2010.V[2].ff' to `_423_'.

            
              renaming `$procdff$2011.V[0].ff' to `_424_'.

            
              renaming `$procdff$2012.V[0].ff' to `_425_'.

            
              renaming `$procdff$2013.V[0].ff' to `_426_'.

            
              renaming `$procdff$2014.V[0].ff' to `_427_'.

            
            Dumping module `\usb_tx_phy'.

            
              renaming `$0\TxReady_o[0:0]' to `_000_'.

            
              renaming `$0\append_eop[0:0]' to `_001_'.

            
              renaming `$0\append_eop_sync1[0:0]' to `_002_'.

            
              renaming `$0\append_eop_sync2[0:0]' to `_003_'.

            
              renaming `$0\append_eop_sync3[0:0]' to `_004_'.

            
              renaming `$0\append_eop_sync4[0:0]' to `_005_'.

            
              renaming `$0\bit_cnt[2:0]' to `_006_'.

            
              renaming `$0\data_done[0:0]' to `_007_'.

            
              renaming `$0\hold_reg[7:0]' to `_008_'.

            
              renaming `$0\one_cnt[2:0]' to `_009_'.

            
              renaming `$0\sd_bs_o[0:0]' to `_010_'.

            
              renaming `$0\sd_nrzi_o[0:0]' to `_011_'.

            
              renaming `$0\sd_raw_o[0:0]' to `_012_'.

            
              renaming `$0\sft_done[0:0]' to `_013_'.

            
              renaming `$0\state[2:0]' to `_014_'.

            
              renaming `$0\tx_ip[0:0]' to `_015_'.

            
              renaming `$0\tx_ip_sync[0:0]' to `_016_'.

            
              renaming `$0\txdn[0:0]' to `_017_'.

            
              renaming `$0\txdp[0:0]' to `_018_'.

            
              renaming `$0\txoe[0:0]' to `_019_'.

            
              renaming `$0\txoe_r1[0:0]' to `_020_'.

            
              renaming `$0\txoe_r2[0:0]' to `_021_'.

            
              renaming `$abc$2138$g000' to `_186_'.

            
              renaming `$abc$2138$g001' to `_187_'.

            
              renaming `$abc$2138$g002' to `_188_'.

            
              renaming `$abc$2138$g003' to `_189_'.

            
              renaming `$abc$2138$g004' to `_190_'.

            
              renaming `$abc$2138$g005' to `_191_'.

            
              renaming `$abc$2138$g006' to `_192_'.

            
              renaming `$abc$2138$g007' to `_193_'.

            
              renaming `$abc$2138$g008' to `_194_'.

            
              renaming `$abc$2138$g009' to `_195_'.

            
              renaming `$abc$2138$g010' to `_196_'.

            
              renaming `$abc$2138$g011' to `_197_'.

            
              renaming `$abc$2138$g012' to `_198_'.

            
              renaming `$abc$2138$g013' to `_199_'.

            
              renaming `$abc$2138$g014' to `_200_'.

            
              renaming `$abc$2138$g015' to `_201_'.

            
              renaming `$abc$2138$g016' to `_202_'.

            
              renaming `$abc$2138$g017' to `_203_'.

            
              renaming `$abc$2138$g018' to `_204_'.

            
              renaming `$abc$2138$g019' to `_205_'.

            
              renaming `$abc$2138$g020' to `_206_'.

            
              renaming `$abc$2138$g021' to `_207_'.

            
              renaming `$abc$2138$g022' to `_208_'.

            
              renaming `$abc$2138$g023' to `_209_'.

            
              renaming `$abc$2138$g024' to `_210_'.

            
              renaming `$abc$2138$g025' to `_211_'.

            
              renaming `$abc$2138$g026' to `_212_'.

            
              renaming `$abc$2138$g027' to `_213_'.

            
              renaming `$abc$2138$g028' to `_214_'.

            
              renaming `$abc$2138$g029' to `_215_'.

            
              renaming `$abc$2138$g030' to `_216_'.

            
              renaming `$abc$2138$g031' to `_217_'.

            
              renaming `$abc$2138$g032' to `_218_'.

            
              renaming `$abc$2138$g033' to `_219_'.

            
              renaming `$abc$2138$g034' to `_220_'.

            
              renaming `$abc$2138$g035' to `_221_'.

            
              renaming `$abc$2138$g036' to `_222_'.

            
              renaming `$abc$2138$g037' to `_223_'.

            
              renaming `$abc$2138$g038' to `_224_'.

            
              renaming `$abc$2138$g039' to `_225_'.

            
              renaming `$abc$2138$g040' to `_226_'.

            
              renaming `$abc$2138$g041' to `_227_'.

            
              renaming `$abc$2138$g042' to `_228_'.

            
              renaming `$abc$2138$g043' to `_229_'.

            
              renaming `$abc$2138$g044' to `_230_'.

            
              renaming `$abc$2138$g045' to `_231_'.

            
              renaming `$abc$2138$g046' to `_232_'.

            
              renaming `$abc$2138$g047' to `_233_'.

            
              renaming `$abc$2138$g048' to `_234_'.

            
              renaming `$abc$2138$g049' to `_235_'.

            
              renaming `$abc$2138$g050' to `_236_'.

            
              renaming `$abc$2138$g051' to `_237_'.

            
              renaming `$abc$2138$g052' to `_238_'.

            
              renaming `$abc$2138$g053' to `_239_'.

            
              renaming `$abc$2138$g054' to `_240_'.

            
              renaming `$abc$2138$g055' to `_241_'.

            
              renaming `$abc$2138$g056' to `_242_'.

            
              renaming `$abc$2138$g057' to `_243_'.

            
              renaming `$abc$2138$g058' to `_244_'.

            
              renaming `$abc$2138$g059' to `_245_'.

            
              renaming `$abc$2138$g060' to `_246_'.

            
              renaming `$abc$2138$g061' to `_247_'.

            
              renaming `$abc$2138$g062' to `_248_'.

            
              renaming `$abc$2138$g063' to `_249_'.

            
              renaming `$abc$2138$g064' to `_250_'.

            
              renaming `$abc$2138$g065' to `_251_'.

            
              renaming `$abc$2138$g066' to `_252_'.

            
              renaming `$abc$2138$g067' to `_253_'.

            
              renaming `$abc$2138$g068' to `_254_'.

            
              renaming `$abc$2138$g069' to `_255_'.

            
              renaming `$abc$2138$g070' to `_256_'.

            
              renaming `$abc$2138$g071' to `_257_'.

            
              renaming `$abc$2138$g072' to `_258_'.

            
              renaming `$abc$2138$g073' to `_259_'.

            
              renaming `$abc$2138$g074' to `_260_'.

            
              renaming `$abc$2138$g075' to `_261_'.

            
              renaming `$abc$2138$g076' to `_262_'.

            
              renaming `$abc$2138$g077' to `_263_'.

            
              renaming `$abc$2138$g078' to `_264_'.

            
              renaming `$abc$2138$g079' to `_265_'.

            
              renaming `$abc$2138$g080' to `_266_'.

            
              renaming `$abc$2138$g081' to `_267_'.

            
              renaming `$abc$2138$g082' to `_268_'.

            
              renaming `$abc$2138$g083' to `_269_'.

            
              renaming `$abc$2138$g084' to `_270_'.

            
              renaming `$abc$2138$g085' to `_271_'.

            
              renaming `$abc$2138$g086' to `_272_'.

            
              renaming `$abc$2138$g087' to `_273_'.

            
              renaming `$abc$2138$g088' to `_274_'.

            
              renaming `$abc$2138$g089' to `_275_'.

            
              renaming `$abc$2138$g090' to `_276_'.

            
              renaming `$abc$2138$g091' to `_277_'.

            
              renaming `$abc$2138$g092' to `_278_'.

            
              renaming `$abc$2138$g093' to `_279_'.

            
              renaming `$abc$2138$g094' to `_280_'.

            
              renaming `$abc$2138$g095' to `_281_'.

            
              renaming `$abc$2138$g096' to `_282_'.

            
              renaming `$abc$2138$g097' to `_283_'.

            
              renaming `$abc$2138$g098' to `_284_'.

            
              renaming `$abc$2138$g099' to `_285_'.

            
              renaming `$abc$2138$g100' to `_286_'.

            
              renaming `$abc$2138$g101' to `_287_'.

            
              renaming `$abc$2138$g102' to `_288_'.

            
              renaming `$abc$2138$g103' to `_289_'.

            
              renaming `$abc$2138$g104' to `_290_'.

            
              renaming `$abc$2138$g105' to `_291_'.

            
              renaming `$abc$2138$g106' to `_292_'.

            
              renaming `$abc$2138$g107' to `_293_'.

            
              renaming `$abc$2138$g108' to `_294_'.

            
              renaming `$abc$2138$g109' to `_295_'.

            
              renaming `$abc$2138$g110' to `_296_'.

            
              renaming `$abc$2138$g111' to `_297_'.

            
              renaming `$abc$2138$g112' to `_298_'.

            
              renaming `$abc$2138$g113' to `_299_'.

            
              renaming `$abc$2138$g114' to `_300_'.

            
              renaming `$abc$2138$g115' to `_301_'.

            
              renaming `$abc$2138$g116' to `_302_'.

            
              renaming `$abc$2138$g117' to `_303_'.

            
              renaming `$abc$2138$g118' to `_304_'.

            
              renaming `$abc$2138$g119' to `_305_'.

            
              renaming `$abc$2138$g120' to `_306_'.

            
              renaming `$abc$2138$g121' to `_307_'.

            
              renaming `$abc$2138$g122' to `_308_'.

            
              renaming `$abc$2138$g123' to `_309_'.

            
              renaming `$abc$2138$g124' to `_310_'.

            
              renaming `$abc$2138$g125' to `_311_'.

            
              renaming `$abc$2138$g126' to `_312_'.

            
              renaming `$abc$2138$g127' to `_313_'.

            
              renaming `$abc$2138$g128' to `_314_'.

            
              renaming `$abc$2138$g129' to `_315_'.

            
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            READY.