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foss-fpga-tools
/
third_party
/
Surelog
/
356a4bf2123fc606ca19fbed9b9c535f149fdec5
/
.
/
SVIncCompil
/
Testcases
/
YosysTestSuite
/
arch
/
common
/
tribuf.v
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module
tristate
(
en
,
i
,
o
);
input en
;
input i
;
output reg o
;
always
@(
en
or
i
)
o
<=
(
en
)?
i
:
1
'bZ;
endmodule
