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foss-fpga-tools
/
third_party
/
Surelog
/
356a4bf2123fc606ca19fbed9b9c535f149fdec5
/
.
/
SVIncCompil
/
Testcases
/
YosysTestSuite
/
errors
/
syntax_err09.v
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module
a
(
input wire x
=
1
'b0);
endmodule
